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sync for different clock 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-25 17:10:11 +08:00
parent 43aca8195c
commit 02bcee9aa9
1 changed files with 92 additions and 18 deletions
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110
rtl/debug/jtag_top.v
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@ -14,9 +14,14 @@
limitations under the License.
*/
`include "../core/defines.v"
// JTAG顶层模块
// 涉及跨时钟域传输，这里采用打两拍的方式进行同步
module jtag_top(
input wire clk,
input wire jtag_rst_n,
input wire jtag_pin_TCK,
@ -24,18 +29,18 @@ module jtag_top(
input wire jtag_pin_TDI,
output wire jtag_pin_TDO,
output wire reg_we_o,
output wire[4:0] reg_addr_o,
output wire[31:0] reg_wdata_o,
output reg reg_we_o,
output reg[4:0] reg_addr_o,
output reg[31:0] reg_wdata_o,
input wire[31:0] reg_rdata_i,
output wire mem_we_o,
output wire[31:0] mem_addr_o,
output wire[31:0] mem_wdata_o,
output reg mem_we_o,
output reg[31:0] mem_addr_o,
output reg[31:0] mem_wdata_o,
input wire[31:0] mem_rdata_i,
output wire op_req_o,
output reg op_req_o,
output wire halt_req_o,
output wire reset_req_o
output reg halt_req_o,
output reg reset_req_o
);
@ -52,7 +57,76 @@ module jtag_top(
// jtag_dm
wire dm_is_busy;
wire[DM_RESP_BITS - 1:0] dm_resp_data;
wire dm_reg_we_o;
wire[4:0] dm_reg_addr_o;
wire[31:0] dm_reg_wdata_o;
wire dm_mem_we_o;
wire[31:0] dm_mem_addr_o;
wire[31:0] dm_mem_wdata_o;
wire dm_op_req_o;
wire dm_halt_req_o;
wire dm_reset_req_o;
reg tmp_reg_we_o;
reg[4:0] tmp_reg_addr_o;
reg[31:0] tmp_reg_wdata_o;
reg tmp_mem_we_o;
reg[31:0] tmp_mem_addr_o;
reg[31:0] tmp_mem_wdata_o;
reg tmp_op_req_o;
reg tmp_halt_req_o;
reg tmp_reset_req_o;
// 打第一拍
always @ (posedge clk) begin
if (!jtag_rst_n) begin
tmp_reg_we_o <= `WriteDisable;
tmp_reg_addr_o <= `ZeroReg;
tmp_reg_wdata_o <= `ZeroWord;
tmp_mem_we_o <= `WriteDisable;
tmp_mem_addr_o <= `ZeroWord;
tmp_mem_wdata_o <= `ZeroWord;
tmp_op_req_o <= 1'b0;
tmp_halt_req_o <= 1'b0;
tmp_reset_req_o <= 1'b0;
end else begin
tmp_reg_we_o <= dm_reg_we_o;
tmp_reg_addr_o <= dm_reg_addr_o;
tmp_reg_wdata_o <= dm_reg_wdata_o;
tmp_mem_we_o <= dm_mem_we_o;
tmp_mem_addr_o <= dm_mem_addr_o;
tmp_mem_wdata_o <= dm_mem_wdata_o;
tmp_op_req_o <= dm_op_req_o;
tmp_halt_req_o <= dm_halt_req_o;
tmp_reset_req_o <= dm_reset_req_o;
end
end
// 打第二拍
always @ (posedge clk) begin
if (!jtag_rst_n) begin
reg_we_o <= `WriteDisable;
reg_addr_o <= `ZeroReg;
reg_wdata_o <= `ZeroWord;
mem_we_o <= `WriteDisable;
mem_addr_o <= `ZeroWord;
mem_wdata_o <= `ZeroWord;
op_req_o <= 1'b0;
halt_req_o <= 1'b0;
reset_req_o <= 1'b0;
end else begin
reg_we_o <= tmp_reg_we_o;
reg_addr_o <= tmp_reg_addr_o;
reg_wdata_o <= tmp_reg_wdata_o;
mem_we_o <= tmp_mem_we_o;
mem_addr_o <= tmp_mem_addr_o;
mem_wdata_o <= tmp_mem_wdata_o;
op_req_o <= tmp_op_req_o;
halt_req_o <= tmp_halt_req_o;
reset_req_o <= tmp_reset_req_o;
end
end
jtag_driver u_jtag_driver(
.rst_n(jtag_rst_n),
@ -73,17 +147,17 @@ module jtag_top(
.dtm_req_data(dtm_req_data),
.dm_is_busy(dm_is_busy),
.dm_resp_data(dm_resp_data),
.dm_reg_we(reg_we_o),
.dm_reg_addr(reg_addr_o),
.dm_reg_wdata(reg_wdata_o),
.dm_reg_we(dm_reg_we_o),
.dm_reg_addr(dm_reg_addr_o),
.dm_reg_wdata(dm_reg_wdata_o),
.dm_reg_rdata(reg_rdata_i),
.dm_mem_we(mem_we_o),
.dm_mem_addr(mem_addr_o),
.dm_mem_wdata(mem_wdata_o),
.dm_mem_we(dm_mem_we_o),
.dm_mem_addr(dm_mem_addr_o),
.dm_mem_wdata(dm_mem_wdata_o),
.dm_mem_rdata(mem_rdata_i),
.dm_op_req(op_req_o),
.dm_halt_req(halt_req_o),
.dm_reset_req(reset_req_o)
.dm_op_req(dm_op_req_o),
.dm_halt_req(dm_halt_req_o),
.dm_reset_req(dm_reset_req_o)
);
endmodule