diff --git a/tests/riscv-compliance/Makefile b/tests/riscv-compliance/Makefile
index 0147ebc..e60dbf9 100644
--- a/tests/riscv-compliance/Makefile
+++ b/tests/riscv-compliance/Makefile
@@ -17,10 +17,12 @@ default: all
 all:
 	$(MAKE) RISCV_TARGET=$(RISCV_TARGET) RISCV_DEVICE=rv32i RISCV_PREFIX=$(RISCV_PREFIX) RISCV_ISA=rv32i run -C $(ROOTDIR)/riscv-test-suite/rv32i
 	$(MAKE) RISCV_TARGET=$(RISCV_TARGET) RISCV_DEVICE=rv32im RISCV_PREFIX=$(RISCV_PREFIX) RISCV_ISA=rv32im run -C $(ROOTDIR)/riscv-test-suite/rv32im
-
-
+	$(MAKE) RISCV_TARGET=$(RISCV_TARGET) RISCV_DEVICE=rv32Zicsr RISCV_PREFIX=$(RISCV_PREFIX) RISCV_ISA=rv32Zicsr run -C $(ROOTDIR)/riscv-test-suite/rv32Zicsr
+	$(MAKE) RISCV_TARGET=$(RISCV_TARGET) RISCV_DEVICE=rv32Zifencei RISCV_PREFIX=$(RISCV_PREFIX) RISCV_ISA=rv32Zifencei run -C $(ROOTDIR)/riscv-test-suite/rv32Zifencei
 
 clean:
 	clean -C $(ROOTDIR)/riscv-test-suite/rv32i
 	clean -C $(ROOTDIR)/riscv-test-suite/rv32im
+	clean -C $(ROOTDIR)/riscv-test-suite/rv32Zicsr
+	clean -C $(ROOTDIR)/riscv-test-suite/rv32Zifencei
 
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf
new file mode 100644
index 0000000..fe621ac
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf.bin b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf.bin
new file mode 100644
index 0000000..ec8b056
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf.objdump
new file mode 100644
index 0000000..537a4c6
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf.objdump
@@ -0,0 +1,246 @@
+
+D:/gitee/tmp/tinyriscv/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRC-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002797          	auipc	a5,0x2
+  84:	f8078793          	addi	a5,a5,-128 # 2000 <begin_signature>
+  88:	00100093          	li	ra,1
+  8c:	00000113          	li	sp,0
+  90:	7ff101b7          	lui	gp,0x7ff10
+  94:	fff18193          	addi	gp,gp,-1 # 7ff0ffff <_end+0x7ff0ddfb>
+  98:	80000237          	lui	tp,0x80000
+  9c:	fff00293          	li	t0,-1
+  a0:	34029073          	csrw	mscratch,t0
+  a4:	3400b0f3          	csrrc	ra,mscratch,ra
+  a8:	340290f3          	csrrw	ra,mscratch,t0
+  ac:	34013173          	csrrc	sp,mscratch,sp
+  b0:	34029173          	csrrw	sp,mscratch,t0
+  b4:	3401b1f3          	csrrc	gp,mscratch,gp
+  b8:	340291f3          	csrrw	gp,mscratch,t0
+  bc:	34023273          	csrrc	tp,mscratch,tp
+  c0:	34029273          	csrrw	tp,mscratch,t0
+  c4:	3402b2f3          	csrrc	t0,mscratch,t0
+  c8:	340012f3          	csrrw	t0,mscratch,zero
+  cc:	0007a023          	sw	zero,0(a5)
+  d0:	0017a223          	sw	ra,4(a5)
+  d4:	0027a423          	sw	sp,8(a5)
+  d8:	0037a623          	sw	gp,12(a5)
+  dc:	0047a823          	sw	tp,16(a5)
+  e0:	0057aa23          	sw	t0,20(a5)
+  e4:	00002297          	auipc	t0,0x2
+  e8:	f3428293          	addi	t0,t0,-204 # 2018 <test_A2_res>
+  ec:	00100593          	li	a1,1
+  f0:	00000613          	li	a2,0
+  f4:	7ff106b7          	lui	a3,0x7ff10
+  f8:	fff68693          	addi	a3,a3,-1 # 7ff0ffff <_end+0x7ff0ddfb>
+  fc:	80000737          	lui	a4,0x80000
+ 100:	fff00793          	li	a5,-1
+ 104:	34079073          	csrw	mscratch,a5
+ 108:	3405b5f3          	csrrc	a1,mscratch,a1
+ 10c:	34063673          	csrrc	a2,mscratch,a2
+ 110:	3406b6f3          	csrrc	a3,mscratch,a3
+ 114:	34073773          	csrrc	a4,mscratch,a4
+ 118:	3407b7f3          	csrrc	a5,mscratch,a5
+ 11c:	34003873          	csrrc	a6,mscratch,zero
+ 120:	00b2a023          	sw	a1,0(t0)
+ 124:	00c2a223          	sw	a2,4(t0)
+ 128:	00d2a423          	sw	a3,8(t0)
+ 12c:	00e2a623          	sw	a4,12(t0)
+ 130:	00f2a823          	sw	a5,16(t0)
+ 134:	0102aa23          	sw	a6,20(t0)
+ 138:	00002d17          	auipc	s10,0x2
+ 13c:	ef8d0d13          	addi	s10,s10,-264 # 2030 <test_B_res>
+ 140:	12345ab7          	lui	s5,0x12345
+ 144:	678a8a93          	addi	s5,s5,1656 # 12345678 <_end+0x12343474>
+ 148:	fff00a13          	li	s4,-1
+ 14c:	340a1073          	csrw	mscratch,s4
+ 150:	340abb73          	csrrc	s6,mscratch,s5
+ 154:	340b3af3          	csrrc	s5,mscratch,s6
+ 158:	340a1bf3          	csrrw	s7,mscratch,s4
+ 15c:	340bbc73          	csrrc	s8,mscratch,s7
+ 160:	34003cf3          	csrrc	s9,mscratch,zero
+ 164:	015d2023          	sw	s5,0(s10)
+ 168:	016d2223          	sw	s6,4(s10)
+ 16c:	017d2423          	sw	s7,8(s10)
+ 170:	018d2623          	sw	s8,12(s10)
+ 174:	019d2823          	sw	s9,16(s10)
+ 178:	00002097          	auipc	ra,0x2
+ 17c:	ecc08093          	addi	ra,ra,-308 # 2044 <test_C_res>
+ 180:	42727f37          	lui	t5,0x42727
+ 184:	e6ff0f13          	addi	t5,t5,-401 # 42726e6f <_end+0x42724c6b>
+ 188:	340f1073          	csrw	mscratch,t5
+ 18c:	340f3073          	csrc	mscratch,t5
+ 190:	0000a023          	sw	zero,0(ra)
+ 194:	01e0a223          	sw	t5,4(ra)
+ 198:	00002117          	auipc	sp,0x2
+ 19c:	eb410113          	addi	sp,sp,-332 # 204c <test_D_res>
+ 1a0:	f7ff9fb7          	lui	t6,0xf7ff9
+ 1a4:	818f8f93          	addi	t6,t6,-2024 # f7ff8818 <_end+0xf7ff6614>
+ 1a8:	340f9073          	csrw	mscratch,t6
+ 1ac:	34003073          	csrc	mscratch,zero
+ 1b0:	34003073          	csrc	mscratch,zero
+ 1b4:	34003ff3          	csrrc	t6,mscratch,zero
+ 1b8:	00012023          	sw	zero,0(sp)
+ 1bc:	01f12223          	sw	t6,4(sp)
+ 1c0:	00002117          	auipc	sp,0x2
+ 1c4:	e9410113          	addi	sp,sp,-364 # 2054 <test_E_res>
+ 1c8:	fff00213          	li	tp,-1
+ 1cc:	963852b7          	lui	t0,0x96385
+ 1d0:	27428293          	addi	t0,t0,628 # 96385274 <_end+0x96383070>
+ 1d4:	321653b7          	lui	t2,0x32165
+ 1d8:	49838393          	addi	t2,t2,1176 # 32165498 <_end+0x32163294>
+ 1dc:	34021073          	csrw	mscratch,tp
+ 1e0:	3402b2f3          	csrrc	t0,mscratch,t0
+ 1e4:	3403b3f3          	csrrc	t2,mscratch,t2
+ 1e8:	34043473          	csrrc	s0,mscratch,s0
+ 1ec:	00512023          	sw	t0,0(sp)
+ 1f0:	00712223          	sw	t2,4(sp)
+ 1f4:	00812423          	sw	s0,8(sp)
+ 1f8:	00002297          	auipc	t0,0x2
+ 1fc:	e0828293          	addi	t0,t0,-504 # 2000 <begin_signature>
+ 200:	10000337          	lui	t1,0x10000
+ 204:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 208:	00532023          	sw	t0,0(t1)
+ 20c:	00002297          	auipc	t0,0x2
+ 210:	e5428293          	addi	t0,t0,-428 # 2060 <end_signature>
+ 214:	10000337          	lui	t1,0x10000
+ 218:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 21c:	00532023          	sw	t0,0(t1)
+ 220:	00100293          	li	t0,1
+ 224:	10000337          	lui	t1,0x10000
+ 228:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 22c:	00532023          	sw	t0,0(t1)
+ 230:	00000013          	nop
+ 234:	00100193          	li	gp,1
+ 238:	00000073          	ecall
+
+0000023c <end_testcode>:
+ 23c:	c0001073          	unimp
+ 240:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_A2_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+
+00002030 <test_B_res>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+
+00002044 <test_C_res>:
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+
+0000204c <test_D_res>:
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+
+00002054 <test_E_res>:
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+
+00002060 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf
new file mode 100644
index 0000000..8eab066
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf.bin
new file mode 100644
index 0000000..d878d8a
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf.objdump
new file mode 100644
index 0000000..6bb9320
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf.objdump
@@ -0,0 +1,175 @@
+
+D:/gitee/tmp/tinyriscv/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRCI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002797          	auipc	a5,0x2
+  84:	f8078793          	addi	a5,a5,-128 # 2000 <begin_signature>
+  88:	fff00413          	li	s0,-1
+  8c:	34041073          	csrw	mscratch,s0
+  90:	3400f0f3          	csrrci	ra,mscratch,1
+  94:	340410f3          	csrrw	ra,mscratch,s0
+  98:	34007173          	csrrci	sp,mscratch,0
+  9c:	34041173          	csrrw	sp,mscratch,s0
+  a0:	340ff1f3          	csrrci	gp,mscratch,31
+  a4:	340411f3          	csrrw	gp,mscratch,s0
+  a8:	34087273          	csrrci	tp,mscratch,16
+  ac:	34041273          	csrrw	tp,mscratch,s0
+  b0:	3407f2f3          	csrrci	t0,mscratch,15
+  b4:	340412f3          	csrrw	t0,mscratch,s0
+  b8:	0007a023          	sw	zero,0(a5)
+  bc:	0017a223          	sw	ra,4(a5)
+  c0:	0027a423          	sw	sp,8(a5)
+  c4:	0037a623          	sw	gp,12(a5)
+  c8:	0047a823          	sw	tp,16(a5)
+  cc:	0057aa23          	sw	t0,20(a5)
+  d0:	0087ac23          	sw	s0,24(a5)
+  d4:	00002297          	auipc	t0,0x2
+  d8:	f4828293          	addi	t0,t0,-184 # 201c <test_A2_res>
+  dc:	fff00413          	li	s0,-1
+  e0:	34041073          	csrw	mscratch,s0
+  e4:	3400f5f3          	csrrci	a1,mscratch,1
+  e8:	34007673          	csrrci	a2,mscratch,0
+  ec:	340ff6f3          	csrrci	a3,mscratch,31
+  f0:	34087773          	csrrci	a4,mscratch,16
+  f4:	3407f7f3          	csrrci	a5,mscratch,15
+  f8:	34007873          	csrrci	a6,mscratch,0
+  fc:	00b2a023          	sw	a1,0(t0)
+ 100:	00c2a223          	sw	a2,4(t0)
+ 104:	00d2a423          	sw	a3,8(t0)
+ 108:	00e2a623          	sw	a4,12(t0)
+ 10c:	00f2a823          	sw	a5,16(t0)
+ 110:	0102aa23          	sw	a6,20(t0)
+ 114:	0082ac23          	sw	s0,24(t0)
+ 118:	00002097          	auipc	ra,0x2
+ 11c:	f2008093          	addi	ra,ra,-224 # 2038 <test_B_res>
+ 120:	32165a37          	lui	s4,0x32165
+ 124:	498a0a13          	addi	s4,s4,1176 # 32165498 <_end+0x32163294>
+ 128:	340a1073          	csrw	mscratch,s4
+ 12c:	3407f073          	csrci	mscratch,15
+ 130:	340a1a73          	csrrw	s4,mscratch,s4
+ 134:	0000a023          	sw	zero,0(ra)
+ 138:	0140a223          	sw	s4,4(ra)
+ 13c:	00002297          	auipc	t0,0x2
+ 140:	ec428293          	addi	t0,t0,-316 # 2000 <begin_signature>
+ 144:	10000337          	lui	t1,0x10000
+ 148:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 14c:	00532023          	sw	t0,0(t1)
+ 150:	00002297          	auipc	t0,0x2
+ 154:	ef028293          	addi	t0,t0,-272 # 2040 <end_signature>
+ 158:	10000337          	lui	t1,0x10000
+ 15c:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 160:	00532023          	sw	t0,0(t1)
+ 164:	00100293          	li	t0,1
+ 168:	10000337          	lui	t1,0x10000
+ 16c:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 170:	00532023          	sw	t0,0(t1)
+ 174:	00000013          	nop
+ 178:	00100193          	li	gp,1
+ 17c:	00000073          	ecall
+
+00000180 <end_testcode>:
+ 180:	c0001073          	unimp
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+
+0000201c <test_A2_res>:
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+
+00002038 <test_B_res>:
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf
new file mode 100644
index 0000000..e7c5b51
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf.bin b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf.bin
new file mode 100644
index 0000000..9fc2300
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf.objdump
new file mode 100644
index 0000000..cab029f
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf.objdump
@@ -0,0 +1,243 @@
+
+D:/gitee/tmp/tinyriscv/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRS-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002797          	auipc	a5,0x2
+  84:	f8078793          	addi	a5,a5,-128 # 2000 <begin_signature>
+  88:	00100093          	li	ra,1
+  8c:	00000113          	li	sp,0
+  90:	7ff101b7          	lui	gp,0x7ff10
+  94:	fff18193          	addi	gp,gp,-1 # 7ff0ffff <_end+0x7ff0ddfb>
+  98:	80000237          	lui	tp,0x80000
+  9c:	fff00293          	li	t0,-1
+  a0:	34001073          	csrw	mscratch,zero
+  a4:	3400a0f3          	csrrs	ra,mscratch,ra
+  a8:	340010f3          	csrrw	ra,mscratch,zero
+  ac:	34012173          	csrrs	sp,mscratch,sp
+  b0:	34001173          	csrrw	sp,mscratch,zero
+  b4:	3401a1f3          	csrrs	gp,mscratch,gp
+  b8:	340011f3          	csrrw	gp,mscratch,zero
+  bc:	34022273          	csrrs	tp,mscratch,tp
+  c0:	34001273          	csrrw	tp,mscratch,zero
+  c4:	3402a2f3          	csrrs	t0,mscratch,t0
+  c8:	340012f3          	csrrw	t0,mscratch,zero
+  cc:	0007a023          	sw	zero,0(a5)
+  d0:	0017a223          	sw	ra,4(a5)
+  d4:	0027a423          	sw	sp,8(a5)
+  d8:	0037a623          	sw	gp,12(a5)
+  dc:	0047a823          	sw	tp,16(a5)
+  e0:	0057aa23          	sw	t0,20(a5)
+  e4:	00002297          	auipc	t0,0x2
+  e8:	f3428293          	addi	t0,t0,-204 # 2018 <test_A2_res>
+  ec:	00100593          	li	a1,1
+  f0:	00000613          	li	a2,0
+  f4:	7ff106b7          	lui	a3,0x7ff10
+  f8:	fff68693          	addi	a3,a3,-1 # 7ff0ffff <_end+0x7ff0ddfb>
+  fc:	80000737          	lui	a4,0x80000
+ 100:	fff00793          	li	a5,-1
+ 104:	34001073          	csrw	mscratch,zero
+ 108:	3405a5f3          	csrrs	a1,mscratch,a1
+ 10c:	34062673          	csrrs	a2,mscratch,a2
+ 110:	3406a6f3          	csrrs	a3,mscratch,a3
+ 114:	34072773          	csrrs	a4,mscratch,a4
+ 118:	3407a7f3          	csrrs	a5,mscratch,a5
+ 11c:	34002873          	csrr	a6,mscratch
+ 120:	00b2a023          	sw	a1,0(t0)
+ 124:	00c2a223          	sw	a2,4(t0)
+ 128:	00d2a423          	sw	a3,8(t0)
+ 12c:	00e2a623          	sw	a4,12(t0)
+ 130:	00f2a823          	sw	a5,16(t0)
+ 134:	0102aa23          	sw	a6,20(t0)
+ 138:	00002d17          	auipc	s10,0x2
+ 13c:	ef8d0d13          	addi	s10,s10,-264 # 2030 <test_B_res>
+ 140:	12345ab7          	lui	s5,0x12345
+ 144:	678a8a93          	addi	s5,s5,1656 # 12345678 <_end+0x12343474>
+ 148:	34001073          	csrw	mscratch,zero
+ 14c:	340aab73          	csrrs	s6,mscratch,s5
+ 150:	340b2bf3          	csrrs	s7,mscratch,s6
+ 154:	34001bf3          	csrrw	s7,mscratch,zero
+ 158:	340bac73          	csrrs	s8,mscratch,s7
+ 15c:	34002cf3          	csrr	s9,mscratch
+ 160:	015d2023          	sw	s5,0(s10)
+ 164:	016d2223          	sw	s6,4(s10)
+ 168:	017d2423          	sw	s7,8(s10)
+ 16c:	018d2623          	sw	s8,12(s10)
+ 170:	019d2823          	sw	s9,16(s10)
+ 174:	00002097          	auipc	ra,0x2
+ 178:	ed008093          	addi	ra,ra,-304 # 2044 <test_C_res>
+ 17c:	42727f37          	lui	t5,0x42727
+ 180:	e6ff0f13          	addi	t5,t5,-401 # 42726e6f <_end+0x42724c6b>
+ 184:	340f1073          	csrw	mscratch,t5
+ 188:	340f2073          	csrs	mscratch,t5
+ 18c:	0000a023          	sw	zero,0(ra)
+ 190:	01e0a223          	sw	t5,4(ra)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	eb810113          	addi	sp,sp,-328 # 204c <test_D_res>
+ 19c:	f7ff9fb7          	lui	t6,0xf7ff9
+ 1a0:	818f8f93          	addi	t6,t6,-2024 # f7ff8818 <_end+0xf7ff6614>
+ 1a4:	340f9073          	csrw	mscratch,t6
+ 1a8:	34002073          	csrr	zero,mscratch
+ 1ac:	34002073          	csrr	zero,mscratch
+ 1b0:	34002ff3          	csrr	t6,mscratch
+ 1b4:	00012023          	sw	zero,0(sp)
+ 1b8:	01f12223          	sw	t6,4(sp)
+ 1bc:	00002117          	auipc	sp,0x2
+ 1c0:	e9810113          	addi	sp,sp,-360 # 2054 <test_E_res>
+ 1c4:	321653b7          	lui	t2,0x32165
+ 1c8:	49838393          	addi	t2,t2,1176 # 32165498 <_end+0x32163294>
+ 1cc:	963852b7          	lui	t0,0x96385
+ 1d0:	27428293          	addi	t0,t0,628 # 96385274 <_end+0x96383070>
+ 1d4:	34001073          	csrw	mscratch,zero
+ 1d8:	3402a2f3          	csrrs	t0,mscratch,t0
+ 1dc:	3403a3f3          	csrrs	t2,mscratch,t2
+ 1e0:	34042473          	csrrs	s0,mscratch,s0
+ 1e4:	00512023          	sw	t0,0(sp)
+ 1e8:	00712223          	sw	t2,4(sp)
+ 1ec:	00812423          	sw	s0,8(sp)
+ 1f0:	00002297          	auipc	t0,0x2
+ 1f4:	e1028293          	addi	t0,t0,-496 # 2000 <begin_signature>
+ 1f8:	10000337          	lui	t1,0x10000
+ 1fc:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 200:	00532023          	sw	t0,0(t1)
+ 204:	00002297          	auipc	t0,0x2
+ 208:	e5c28293          	addi	t0,t0,-420 # 2060 <end_signature>
+ 20c:	10000337          	lui	t1,0x10000
+ 210:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 214:	00532023          	sw	t0,0(t1)
+ 218:	00100293          	li	t0,1
+ 21c:	10000337          	lui	t1,0x10000
+ 220:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 224:	00532023          	sw	t0,0(t1)
+ 228:	00000013          	nop
+ 22c:	00100193          	li	gp,1
+ 230:	00000073          	ecall
+
+00000234 <end_testcode>:
+ 234:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_A2_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+
+00002030 <test_B_res>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+
+00002044 <test_C_res>:
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+
+0000204c <test_D_res>:
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+
+00002054 <test_E_res>:
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+
+00002060 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf
new file mode 100644
index 0000000..7f7ad94
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf.bin
new file mode 100644
index 0000000..e62f046
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf.objdump
new file mode 100644
index 0000000..06bccd5
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf.objdump
@@ -0,0 +1,174 @@
+
+D:/gitee/tmp/tinyriscv/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRSI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002797          	auipc	a5,0x2
+  84:	f8078793          	addi	a5,a5,-128 # 2000 <begin_signature>
+  88:	34001073          	csrw	mscratch,zero
+  8c:	3400e0f3          	csrrsi	ra,mscratch,1
+  90:	340010f3          	csrrw	ra,mscratch,zero
+  94:	34006173          	csrrsi	sp,mscratch,0
+  98:	34001173          	csrrw	sp,mscratch,zero
+  9c:	340fe1f3          	csrrsi	gp,mscratch,31
+  a0:	340011f3          	csrrw	gp,mscratch,zero
+  a4:	34086273          	csrrsi	tp,mscratch,16
+  a8:	34001273          	csrrw	tp,mscratch,zero
+  ac:	3407e2f3          	csrrsi	t0,mscratch,15
+  b0:	340012f3          	csrrw	t0,mscratch,zero
+  b4:	0007a023          	sw	zero,0(a5)
+  b8:	0017a223          	sw	ra,4(a5)
+  bc:	0027a423          	sw	sp,8(a5)
+  c0:	0037a623          	sw	gp,12(a5)
+  c4:	0047a823          	sw	tp,16(a5)
+  c8:	0057aa23          	sw	t0,20(a5)
+  cc:	00002297          	auipc	t0,0x2
+  d0:	f4c28293          	addi	t0,t0,-180 # 2018 <test_A2_res>
+  d4:	34001073          	csrw	mscratch,zero
+  d8:	3400e5f3          	csrrsi	a1,mscratch,1
+  dc:	34006673          	csrrsi	a2,mscratch,0
+  e0:	340fe6f3          	csrrsi	a3,mscratch,31
+  e4:	34086773          	csrrsi	a4,mscratch,16
+  e8:	3407e7f3          	csrrsi	a5,mscratch,15
+  ec:	34006873          	csrrsi	a6,mscratch,0
+  f0:	0002a023          	sw	zero,0(t0)
+  f4:	00b2a223          	sw	a1,4(t0)
+  f8:	00c2a423          	sw	a2,8(t0)
+  fc:	00d2a623          	sw	a3,12(t0)
+ 100:	00e2a823          	sw	a4,16(t0)
+ 104:	00f2aa23          	sw	a5,20(t0)
+ 108:	0102ac23          	sw	a6,24(t0)
+ 10c:	00002097          	auipc	ra,0x2
+ 110:	f2808093          	addi	ra,ra,-216 # 2034 <test_B_res>
+ 114:	32165a37          	lui	s4,0x32165
+ 118:	498a0a13          	addi	s4,s4,1176 # 32165498 <_end+0x32163294>
+ 11c:	340a1073          	csrw	mscratch,s4
+ 120:	3407e073          	csrsi	mscratch,15
+ 124:	340a1af3          	csrrw	s5,mscratch,s4
+ 128:	0000a023          	sw	zero,0(ra)
+ 12c:	0150a223          	sw	s5,4(ra)
+ 130:	0140a423          	sw	s4,8(ra)
+ 134:	00002297          	auipc	t0,0x2
+ 138:	ecc28293          	addi	t0,t0,-308 # 2000 <begin_signature>
+ 13c:	10000337          	lui	t1,0x10000
+ 140:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 144:	00532023          	sw	t0,0(t1)
+ 148:	00002297          	auipc	t0,0x2
+ 14c:	ef828293          	addi	t0,t0,-264 # 2040 <end_signature>
+ 150:	10000337          	lui	t1,0x10000
+ 154:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 158:	00532023          	sw	t0,0(t1)
+ 15c:	00100293          	li	t0,1
+ 160:	10000337          	lui	t1,0x10000
+ 164:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 168:	00532023          	sw	t0,0(t1)
+ 16c:	00000013          	nop
+ 170:	00100193          	li	gp,1
+ 174:	00000073          	ecall
+
+00000178 <end_testcode>:
+ 178:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_A2_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+
+00002034 <test_B_res>:
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf
new file mode 100644
index 0000000..e168265
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf.bin b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf.bin
new file mode 100644
index 0000000..0e514ef
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf.objdump
new file mode 100644
index 0000000..e43e02e
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf.objdump
@@ -0,0 +1,201 @@
+
+D:/gitee/tmp/tinyriscv/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRW-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002797          	auipc	a5,0x2
+  84:	f8078793          	addi	a5,a5,-128 # 2000 <begin_signature>
+  88:	00100093          	li	ra,1
+  8c:	00000193          	li	gp,0
+  90:	fff00293          	li	t0,-1
+  94:	80000db7          	lui	s11,0x80000
+  98:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+  9c:	80000eb7          	lui	t4,0x80000
+  a0:	34001073          	csrw	mscratch,zero
+  a4:	34009173          	csrrw	sp,mscratch,ra
+  a8:	34019273          	csrrw	tp,mscratch,gp
+  ac:	34029373          	csrrw	t1,mscratch,t0
+  b0:	340d9e73          	csrrw	t3,mscratch,s11
+  b4:	340e9f73          	csrrw	t5,mscratch,t4
+  b8:	34001ff3          	csrrw	t6,mscratch,zero
+  bc:	0027a023          	sw	sp,0(a5)
+  c0:	0047a223          	sw	tp,4(a5)
+  c4:	0067a423          	sw	t1,8(a5)
+  c8:	01c7a623          	sw	t3,12(a5)
+  cc:	01e7a823          	sw	t5,16(a5)
+  d0:	01f7aa23          	sw	t6,20(a5)
+  d4:	00002d17          	auipc	s10,0x2
+  d8:	f44d0d13          	addi	s10,s10,-188 # 2018 <test_B_res>
+  dc:	123450b7          	lui	ra,0x12345
+  e0:	67808093          	addi	ra,ra,1656 # 12345678 <_end+0x12343474>
+  e4:	9abce137          	lui	sp,0x9abce
+  e8:	ef010113          	addi	sp,sp,-272 # 9abcdef0 <_end+0x9abcbcec>
+  ec:	34009073          	csrw	mscratch,ra
+  f0:	340111f3          	csrrw	gp,mscratch,sp
+  f4:	34019273          	csrrw	tp,mscratch,gp
+  f8:	340212f3          	csrrw	t0,mscratch,tp
+  fc:	34001373          	csrrw	t1,mscratch,zero
+ 100:	003d2023          	sw	gp,0(s10)
+ 104:	004d2223          	sw	tp,4(s10)
+ 108:	005d2423          	sw	t0,8(s10)
+ 10c:	006d2623          	sw	t1,12(s10)
+ 110:	00002097          	auipc	ra,0x2
+ 114:	f1808093          	addi	ra,ra,-232 # 2028 <test_C_res>
+ 118:	42727137          	lui	sp,0x42727
+ 11c:	e6f10113          	addi	sp,sp,-401 # 42726e6f <_end+0x42724c6b>
+ 120:	34011073          	csrw	mscratch,sp
+ 124:	34001073          	csrw	mscratch,zero
+ 128:	0000a023          	sw	zero,0(ra)
+ 12c:	00002117          	auipc	sp,0x2
+ 130:	f0010113          	addi	sp,sp,-256 # 202c <test_D_res>
+ 134:	f7ff9db7          	lui	s11,0xf7ff9
+ 138:	818d8d93          	addi	s11,s11,-2024 # f7ff8818 <_end+0xf7ff6614>
+ 13c:	340d9073          	csrw	mscratch,s11
+ 140:	34001073          	csrw	mscratch,zero
+ 144:	34001073          	csrw	mscratch,zero
+ 148:	340012f3          	csrrw	t0,mscratch,zero
+ 14c:	00012023          	sw	zero,0(sp)
+ 150:	00512223          	sw	t0,4(sp)
+ 154:	00002117          	auipc	sp,0x2
+ 158:	ee010113          	addi	sp,sp,-288 # 2034 <test_E_res>
+ 15c:	321653b7          	lui	t2,0x32165
+ 160:	49838393          	addi	t2,t2,1176 # 32165498 <_end+0x32163294>
+ 164:	14726337          	lui	t1,0x14726
+ 168:	83630313          	addi	t1,t1,-1994 # 14725836 <_end+0x14723632>
+ 16c:	963852b7          	lui	t0,0x96385
+ 170:	27428293          	addi	t0,t0,628 # 96385274 <_end+0x96383070>
+ 174:	34031073          	csrw	mscratch,t1
+ 178:	340292f3          	csrrw	t0,mscratch,t0
+ 17c:	340393f3          	csrrw	t2,mscratch,t2
+ 180:	34001473          	csrrw	s0,mscratch,zero
+ 184:	00512023          	sw	t0,0(sp)
+ 188:	00712223          	sw	t2,4(sp)
+ 18c:	00812423          	sw	s0,8(sp)
+ 190:	00002297          	auipc	t0,0x2
+ 194:	e7028293          	addi	t0,t0,-400 # 2000 <begin_signature>
+ 198:	10000337          	lui	t1,0x10000
+ 19c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 1a0:	00532023          	sw	t0,0(t1)
+ 1a4:	00002297          	auipc	t0,0x2
+ 1a8:	e9c28293          	addi	t0,t0,-356 # 2040 <end_signature>
+ 1ac:	10000337          	lui	t1,0x10000
+ 1b0:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 1b4:	00532023          	sw	t0,0(t1)
+ 1b8:	00100293          	li	t0,1
+ 1bc:	10000337          	lui	t1,0x10000
+ 1c0:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 1c4:	00532023          	sw	t0,0(t1)
+ 1c8:	00000013          	nop
+ 1cc:	00100193          	li	gp,1
+ 1d0:	00000073          	ecall
+
+000001d4 <end_testcode>:
+ 1d4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_B_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_C_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+
+0000202c <test_D_res>:
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+
+00002034 <test_E_res>:
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf
new file mode 100644
index 0000000..1010e80
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf.bin
new file mode 100644
index 0000000..28a263d
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf.objdump
new file mode 100644
index 0000000..4c2fce9
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf.objdump
@@ -0,0 +1,132 @@
+
+D:/gitee/tmp/tinyriscv/tests/riscv-compliance/build_generated/rv32Zicsr/I-CSRRWI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002797          	auipc	a5,0x2
+  84:	f8078793          	addi	a5,a5,-128 # 2000 <begin_signature>
+  88:	34001073          	csrw	mscratch,zero
+  8c:	3400d173          	csrrwi	sp,mscratch,1
+  90:	34005273          	csrrwi	tp,mscratch,0
+  94:	340fd373          	csrrwi	t1,mscratch,31
+  98:	3407de73          	csrrwi	t3,mscratch,15
+  9c:	34085f73          	csrrwi	t5,mscratch,16
+  a0:	34005ff3          	csrrwi	t6,mscratch,0
+  a4:	0007a023          	sw	zero,0(a5)
+  a8:	0027a223          	sw	sp,4(a5)
+  ac:	0047a423          	sw	tp,8(a5)
+  b0:	0067a623          	sw	t1,12(a5)
+  b4:	01c7a823          	sw	t3,16(a5)
+  b8:	01e7aa23          	sw	t5,20(a5)
+  bc:	01f7ac23          	sw	t6,24(a5)
+  c0:	00002097          	auipc	ra,0x2
+  c4:	f5c08093          	addi	ra,ra,-164 # 201c <test_B_res>
+  c8:	3407d073          	csrwi	mscratch,15
+  cc:	34005073          	csrwi	mscratch,0
+  d0:	0000a023          	sw	zero,0(ra)
+  d4:	00002297          	auipc	t0,0x2
+  d8:	f2c28293          	addi	t0,t0,-212 # 2000 <begin_signature>
+  dc:	10000337          	lui	t1,0x10000
+  e0:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+  e4:	00532023          	sw	t0,0(t1)
+  e8:	00002297          	auipc	t0,0x2
+  ec:	f3828293          	addi	t0,t0,-200 # 2020 <end_signature>
+  f0:	10000337          	lui	t1,0x10000
+  f4:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+  f8:	00532023          	sw	t0,0(t1)
+  fc:	00100293          	li	t0,1
+ 100:	10000337          	lui	t1,0x10000
+ 104:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 108:	00532023          	sw	t0,0(t1)
+ 10c:	00000013          	nop
+ 110:	00100193          	li	gp,1
+ 114:	00000073          	ecall
+
+00000118 <end_testcode>:
+ 118:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+
+0000201c <test_B_res>:
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+
+00002020 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf b/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf
new file mode 100644
index 0000000..fc26a26
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf.bin b/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf.bin
new file mode 100644
index 0000000..3cd2e52
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf.objdump
new file mode 100644
index 0000000..9620094
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf.objdump
@@ -0,0 +1,133 @@
+
+D:/gitee/tmp/tinyriscv/tests/riscv-compliance/build_generated/rv32Zifencei/I-FENCE.I-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002817          	auipc	a6,0x2
+  84:	f8480813          	addi	a6,a6,-124 # 2004 <test_A_data>
+  88:	00002897          	auipc	a7,0x2
+  8c:	f8888893          	addi	a7,a7,-120 # 2010 <begin_signature>
+  90:	00000193          	li	gp,0
+  94:	00082083          	lw	ra,0(a6)
+  98:	00482103          	lw	sp,4(a6)
+  9c:	00002a17          	auipc	s4,0x2
+  a0:	f64a0a13          	addi	s4,s4,-156 # 2000 <instr_A_src>
+  a4:	00000a97          	auipc	s5,0x0
+  a8:	014a8a93          	addi	s5,s5,20 # b8 <instr_A_dst>
+  ac:	000a2783          	lw	a5,0(s4)
+  b0:	00faa023          	sw	a5,0(s5)
+  b4:	0000100f          	fence.i
+
+000000b8 <instr_A_dst>:
+  b8:	00000137          	lui	sp,0x0
+  bc:	0018a023          	sw	ra,0(a7)
+  c0:	0028a223          	sw	sp,4(a7)
+  c4:	0038a423          	sw	gp,8(a7)
+  c8:	00f8a623          	sw	a5,12(a7)
+  cc:	00002297          	auipc	t0,0x2
+  d0:	f4428293          	addi	t0,t0,-188 # 2010 <begin_signature>
+  d4:	10000337          	lui	t1,0x10000
+  d8:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+  dc:	00532023          	sw	t0,0(t1)
+  e0:	00002297          	auipc	t0,0x2
+  e4:	f4028293          	addi	t0,t0,-192 # 2020 <end_signature>
+  e8:	10000337          	lui	t1,0x10000
+  ec:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+  f0:	00532023          	sw	t0,0(t1)
+  f4:	00100293          	li	t0,1
+  f8:	10000337          	lui	t1,0x10000
+  fc:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 100:	00532023          	sw	t0,0(t1)
+ 104:	00000013          	nop
+ 108:	00100193          	li	gp,1
+ 10c:	00000073          	ecall
+
+00000110 <end_testcode>:
+ 110:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <instr_A_src>:
+    2000:	001101b3          	add	gp,sp,ra
+
+00002004 <test_A_data>:
+    2004:	0030                	addi	a2,sp,8
+    2006:	0000                	unimp
+    2008:	0012                	c.slli	zero,0x4
+    200a:	0000                	unimp
+    200c:	0000                	unimp
+	...
+
+00002010 <begin_signature>:
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+
+00002020 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...