110 lines
3.8 KiB
Python
110 lines
3.8 KiB
Python
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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'''Generate DV code for an IP block'''
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import logging as log
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import os
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from typing import List, Union
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import yaml
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from mako import exceptions # type: ignore
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from mako.lookup import TemplateLookup # type: ignore
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from pkg_resources import resource_filename
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from .ip_block import IpBlock
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from .multi_register import MultiRegister
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from .register import Register
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from .window import Window
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def bcname(esc_if_name: str) -> str:
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'''Get the name of the dv_base_reg_block subclass for this device interface'''
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return esc_if_name + "_reg_block"
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def rcname(esc_if_name: str, r: Union[Register, MultiRegister]) -> str:
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'''Get the name of the dv_base_reg subclass for this register'''
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return '{}_reg_{}'.format(esc_if_name, r.name.lower())
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def mcname(esc_if_name: str, m: Window) -> str:
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'''Get the name of the dv_base_mem subclass for this memory'''
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return '{}_mem_{}'.format(esc_if_name, m.name.lower())
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def miname(m: Window) -> str:
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'''Get the lower-case name of a memory block'''
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return m.name.lower()
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def gen_core_file(outdir: str,
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lblock: str,
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dv_base_prefix: str,
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paths: List[str]) -> None:
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depends = ["lowrisc:dv:dv_base_reg"]
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if dv_base_prefix and dv_base_prefix != "dv_base":
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depends.append("lowrisc:dv:{}_reg".format(dv_base_prefix))
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# Generate a fusesoc core file that points at the files we've just
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# generated.
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core_data = {
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'name': "lowrisc:dv:{}_ral_pkg".format(lblock),
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'filesets': {
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'files_dv': {
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'depend': depends,
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'files': paths,
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'file_type': 'systemVerilogSource'
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},
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},
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'targets': {
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'default': {
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'filesets': [
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'files_dv',
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],
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},
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},
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}
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core_file_path = os.path.join(outdir, lblock + '_ral_pkg.core')
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with open(core_file_path, 'w') as core_file:
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core_file.write('CAPI=2:\n')
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yaml.dump(core_data, core_file, encoding='utf-8')
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def gen_dv(block: IpBlock, dv_base_prefix: str, outdir: str) -> int:
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'''Generate DV files for an IpBlock'''
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lookup = TemplateLookup(directories=[resource_filename('reggen', '.')])
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uvm_reg_tpl = lookup.get_template('uvm_reg.sv.tpl')
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# Generate the RAL package(s). For a device interface with no name we
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# generate the package "<block>_ral_pkg" (writing to <block>_ral_pkg.sv).
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# In any other case, we also need the interface name, giving
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# <block>_<ifname>_ral_pkg.
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generated = []
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lblock = block.name.lower()
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for if_name, rb in block.reg_blocks.items():
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hier_path = '' if block.hier_path is None else block.hier_path + '.'
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if_suffix = '' if if_name is None else '_' + if_name.lower()
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mod_base = lblock + if_suffix
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reg_block_path = hier_path + 'u_reg' + if_suffix
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file_name = mod_base + '_ral_pkg.sv'
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generated.append(file_name)
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reg_top_path = os.path.join(outdir, file_name)
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with open(reg_top_path, 'w', encoding='UTF-8') as fout:
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try:
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fout.write(uvm_reg_tpl.render(rb=rb,
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block=block,
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esc_if_name=mod_base,
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reg_block_path=reg_block_path,
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dv_base_prefix=dv_base_prefix))
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except: # noqa F722 for template Exception handling
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log.error(exceptions.text_error_template().render())
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return 1
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gen_core_file(outdir, lblock, dv_base_prefix, generated)
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return 0
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