tinyriscv/tests/isa/generated/rv32ui-p-sh.verilog

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@00000000
73 50 00 10 97 10 00 00 93 80 C0 FF 13 01 A0 0A
23 90 20 00 03 9F 00 00 93 0E A0 0A 93 01 20 00
63 1E DF 45 97 10 00 00 93 80 C0 FD 37 B1 FF FF
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63 16 DF 41 97 10 00 00 93 80 C0 F8 37 A1 FF FF
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03 9F C0 FF B7 BE FF FF 93 8E 0E A0 93 01 70 00
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13 01 01 AA 23 9F 20 FE 03 9F E0 FF B7 1E 00 00
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97 10 00 00 93 80 00 EB 37 31 00 00 13 01 81 09
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83 12 02 00 B7 3E 00 00 93 8E 8E 09 93 01 B0 00
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@00001000
EF BE EF BE EF BE EF BE EF BE EF BE EF BE EF BE
EF BE EF BE 00 00 00 00 00 00 00 00 00 00 00 00
@00001040
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