tinyriscv/tests/isa/generated/rv32ui-p-sra.verilog

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@00000000
13 0D 00 00 93 0D 00 00 B7 00 00 80 13 01 00 00
33 DF 20 40 B7 0E 00 80 93 01 20 00 63 14 DF 59
B7 00 00 80 13 01 10 00 33 DF 20 40 B7 0E 00 C0
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B7 00 00 80 13 01 E0 00 33 DF 20 40 B7 0E FE FF
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13 01 F0 01 33 DF 20 40 93 0E F0 FF 93 01 60 00
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63 12 DF 4B B7 00 00 80 93 80 F0 FF 13 01 F0 01
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B7 8E 81 81 93 8E 1E 18 93 01 C0 00 63 14 DF 47
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B7 CE C0 C0 93 8E 0E 0C 93 01 D0 00 63 14 DF 45
B7 80 81 81 93 80 10 18 13 01 70 00 33 DF 20 40
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B7 80 81 81 93 80 10 18 13 01 E0 00 33 DF 20 40
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93 80 10 18 13 01 10 FC 33 DF 20 40 B7 CE C0 C0
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93 80 10 18 13 01 70 FC 33 DF 20 40 B7 0E 03 FF
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93 80 10 18 13 01 E0 FC 33 DF 20 40 B7 0E FE FF
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93 80 10 18 13 01 F0 FF 33 DF 20 40 93 0E F0 FF
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B3 D0 20 40 B7 0E 00 FF 93 01 60 01 63 9C D0 33
B7 00 00 80 13 01 E0 00 33 D1 20 40 B7 0E FE FF
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13 02 00 00 B7 00 00 80 13 01 F0 01 13 00 00 00
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13 02 00 00 B7 00 00 80 13 00 00 00 13 01 70 00
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B7 0E FE FF 93 01 00 02 63 1E DF 19 13 02 00 00
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33 DF 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE
93 0E F0 FF 93 01 10 02 63 16 DF 17 13 02 00 00
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93 02 20 00 E3 16 52 FE B7 0E 00 FF 93 01 20 02
63 12 DF 15 13 02 00 00 13 01 E0 00 B7 00 00 80
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13 02 00 00 13 01 F0 01 B7 00 00 80 13 00 00 00
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13 02 00 00 13 01 70 00 13 00 00 00 B7 00 00 80
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B7 0E FE FF 93 01 60 02 63 16 DF 09 13 02 00 00
13 01 F0 01 13 00 00 00 13 00 00 00 B7 00 00 80
33 DF 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE
93 0E F0 FF 93 01 70 02 63 1E DF 05 93 00 F0 00
33 51 10 40 93 0E 00 00 93 01 80 02 63 14 D1 05
93 00 00 02 33 D1 00 40 93 0E 00 02 93 01 90 02
63 1A D1 03 B3 50 00 40 93 0E 00 00 93 01 A0 02
63 92 D0 03 93 00 00 40 37 11 00 00 13 01 01 80
33 D0 20 40 93 0E 00 00 93 01 B0 02 63 14 D0 01
63 18 30 00 93 0D 00 00 13 0D 10 00 6F 00 00 00
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00 00 00 00
@00000600
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