65 lines
1.4 KiB
Systemverilog
65 lines
1.4 KiB
Systemverilog
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register slice conforming to Comportibility guide.
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module prim_subreg #(
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parameter int DW = 32 ,
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parameter SWACCESS = "RW", // {RW, RO, WO, W1C, W1S, W0C, RC}
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parameter logic [DW-1:0] RESVAL = '0 // Reset value
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) (
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input clk_i,
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input rst_ni,
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// From SW: valid for RW, WO, W1C, W1S, W0C, RC
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// In case of RC, Top connects Read Pulse to we
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input we,
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input [DW-1:0] wd,
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// From HW: valid for HRW, HWO
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input de,
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input [DW-1:0] d,
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// output to HW and Reg Read
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output logic qe,
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output logic [DW-1:0] q,
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output logic [DW-1:0] qs
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);
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logic wr_en;
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logic [DW-1:0] wr_data;
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prim_subreg_arb #(
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.DW ( DW ),
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.SWACCESS ( SWACCESS )
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) wr_en_data_arb (
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.we,
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.wd,
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.de,
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.d,
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.q,
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.wr_en,
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.wr_data
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);
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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qe <= 1'b0;
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end else begin
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qe <= we;
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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q <= RESVAL;
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end else if (wr_en) begin
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q <= wr_data;
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end
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end
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assign qs = q;
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endmodule
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