2021-03-31 07:25:22 +00:00
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+incdir+../rtl/core
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../rtl/core/clint.sv
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../rtl/core/csr_reg.sv
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../rtl/core/defines.sv
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../rtl/core/divider.sv
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../rtl/core/exu.sv
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../rtl/core/exu_alu_datapath.sv
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../rtl/core/exu_commit.sv
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../rtl/core/exu_dispatch.sv
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../rtl/core/exu_mem.sv
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../rtl/core/exu_muldiv.sv
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../rtl/core/gpr_reg.sv
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../rtl/core/idu.sv
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../rtl/core/idu_exu.sv
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../rtl/core/ifu.sv
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../rtl/core/ifu_idu.sv
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../rtl/core/pipe_ctrl.sv
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../rtl/core/rst_ctrl.sv
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../rtl/core/tinyriscv_core.sv
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../rtl/core/tracer.sv
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../rtl/debug/jtag_dm.sv
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../rtl/debug/jtag_driver.sv
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../rtl/debug/jtag_top.sv
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../rtl/perips/gpio.sv
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../rtl/perips/ram.sv
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../rtl/perips/rom.sv
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../rtl/perips/timer.sv
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../rtl/perips/uart.sv
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../rtl/sys_bus/rib.sv
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../rtl/top/tinyriscv_soc_top.sv
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../rtl/utils/full_handshake_rx.sv
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../rtl/utils/full_handshake_tx.sv
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../rtl/utils/gen_buf.sv
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../rtl/utils/gen_dff.sv
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../rtl/utils/gen_ram.sv
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../rtl/utils/vld_rdy.sv
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