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tinyriscv/tests/isa/generated/rv32ui-p-auipc.verilog

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tests: isa: add support Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-06-05 07:11:33 +00:00
@00000000
test: use csr_sstatus for test result Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-07-10 06:49:36 +00:00
73 50 00 10 13 00 00 00 17 25 00 00 13 05 C5 71
tests: isa: add support Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-06-05 07:11:33 +00:00
EF 05 40 00 33 05 B5 40 B7 2E 00 00 93 8E 0E 71
93 01 20 00 63 14 D5 03 17 E5 FF FF 13 05 C5 8F
EF 05 40 00 33 05 B5 40 B7 EE FF FF 93 8E 0E 8F
test: use csr_sstatus for test result Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-07-10 06:49:36 +00:00
93 01 30 00 63 14 D5 01 63 16 30 00 73 D0 00 10
6F 00 00 00 73 D0 01 10 6F 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
tests: isa: add support Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-06-05 07:11:33 +00:00
@00000080
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00