589 lines
32 KiB
Coq
589 lines
32 KiB
Coq
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/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// execute and writeback module
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module ex (
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input wire clk,
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input wire rst,
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// from id
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input wire[`SramBus] inst_i, // inst content
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input wire inst_valid_i,
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input wire[`SramAddrBus] inst_addr_i, // inst addr
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input wire reg_we_i,
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input wire[`RegAddrBus] reg_waddr_i,
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// from regs
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input wire[`RegBus] reg1_rdata_i, // reg1 read data
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input wire[`RegBus] reg2_rdata_i, // reg2 read data
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// from sram
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input wire[`SramBus] sram_rdata_i, // ram read data
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// from div
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input wire div_ready_i,
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input wire[`DoubleRegBus] div_result_i,
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// to sram
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output reg[`SramBus] sram_wdata_o, // ram write data
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output reg[`SramAddrBus] sram_raddr_o, // ram read addr
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output reg[`SramAddrBus] sram_waddr_o, // ram write addr
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// to regs
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output reg[`RegBus] reg_wdata_o, // reg write data
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output reg reg_we_o, // reg write enable
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output reg[`RegAddrBus] reg_waddr_o, // reg write addr
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// to div
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output wire[`RegBus] div_dividend_o,
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output wire[`RegBus] div_divisor_o,
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output reg div_start_o,
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// to pc_reg
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output wire hold_flag_o,
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output reg[`RegBus] hold_addr_o,
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// to pc_reg
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output reg jump_flag_o, // if jump or not flag
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output reg[`RegBus] jump_addr_o // jump dest addr
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);
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wire[31:0] sign_extend_tmp;
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wire[4:0] shift_bits;
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wire[1:0] sram_raddr_index;
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wire[1:0] sram_waddr_index;
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wire[`DoubleRegBus] mul_temp;
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wire[`DoubleRegBus] mulh_temp;
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wire[`DoubleRegBus] mulh_temp_invert;
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wire[`DoubleRegBus] mulhsu_temp;
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wire[`DoubleRegBus] mulhsu_temp_invert;
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wire[`RegBus] op1_mul;
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wire[`RegBus] op2_mul;
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reg div_starting;
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reg[4:0] div_rd_reg;
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reg[2:0] div_funct3;
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wire[6:0] opcode;
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wire[2:0] funct3;
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wire[6:0] funct7;
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wire[4:0] rd;
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assign opcode = inst_i[6:0];
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assign funct3 = inst_i[14:12];
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assign funct7 = inst_i[31:25];
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assign rd = inst_i[11:7];
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assign sign_extend_tmp = {{20{inst_i[31]}}, inst_i[31:20]};
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assign shift_bits = inst_i[24:20];
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assign mul_temp = reg1_rdata_i * reg2_rdata_i;
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assign op1_mul = (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
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assign op2_mul = (reg2_rdata_i[31] == 1'b1)? (~reg2_rdata_i + 1): reg2_rdata_i;
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assign mulhsu_temp = op1_mul * reg2_rdata_i;
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assign mulh_temp = op1_mul * op2_mul;
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assign mulhsu_temp_invert = ~mulhsu_temp + 1;
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assign mulh_temp_invert = ~mulh_temp + 1;
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assign sram_raddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11;
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assign sram_waddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11;
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assign div_dividend_o = reg1_rdata_i;
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assign div_divisor_o = reg2_rdata_i;
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assign hold_flag_o = (div_starting == `DivStop) ? `HoldDisable : `HoldEnable;
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always @ (*) begin
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if (rst == `RstEnable) begin
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sram_raddr_o <= `ZeroWord;
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jump_flag_o <= `JumpDisable;
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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end else begin
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if (div_starting == `DivStart) begin
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if (div_ready_i == `DivResultReady) begin
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case (div_funct3)
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`INST_DIV: begin
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[31:0];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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end
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`INST_DIVU: begin
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[31:0];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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end
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`INST_REM: begin
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[63:32];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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end
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`INST_REMU: begin
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[63:32];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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end
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endcase
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end
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end else if (inst_valid_i == `InstValid) begin
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reg_waddr_o <= reg_waddr_i;
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reg_we_o <= reg_we_i;
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case (opcode)
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`INST_TYPE_I: begin
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case (funct3)
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`INST_ADDI: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
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end
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`INST_SLTI: begin
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jump_flag_o <= `JumpDisable;
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if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
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if (reg1_rdata_i < sign_extend_tmp) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin
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reg_wdata_o <= 32'h00000001;
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end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin
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reg_wdata_o <= 32'h00000000;
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end else begin
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if (reg1_rdata_i < sign_extend_tmp) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end
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end
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`INST_SLTIU: begin
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jump_flag_o <= `JumpDisable;
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if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
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if (reg1_rdata_i < sign_extend_tmp) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin
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reg_wdata_o <= 32'h00000000;
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end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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if (reg1_rdata_i < sign_extend_tmp) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end
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end
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`INST_XORI: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]};
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end
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`INST_ORI: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]};
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end
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`INST_ANDI: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]};
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end
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`INST_SLLI: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i << shift_bits;
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end
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`INST_SRI: begin
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jump_flag_o <= `JumpDisable;
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if (inst_i[30] == 1'b1) begin
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reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits);
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end else begin
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reg_wdata_o <= reg1_rdata_i >> shift_bits;
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end
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end
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endcase
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end
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`INST_TYPE_R_M: begin
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if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
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case (funct3)
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`INST_ADD_SUB: begin
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jump_flag_o <= `JumpDisable;
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if (inst_i[30] == 1'b0) begin
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reg_wdata_o <= reg1_rdata_i + reg2_rdata_i;
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end else begin
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reg_wdata_o <= reg1_rdata_i - reg2_rdata_i;
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end
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end
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`INST_SLL: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i << reg2_rdata_i[4:0];
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end
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`INST_SLT: begin
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jump_flag_o <= `JumpDisable;
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if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
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if (reg1_rdata_i < reg2_rdata_i) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
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reg_wdata_o <= 32'h00000001;
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end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
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reg_wdata_o <= 32'h00000000;
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end else begin
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if (reg1_rdata_i < reg2_rdata_i) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end
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end
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`INST_SLTU: begin
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jump_flag_o <= `JumpDisable;
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if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
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if (reg1_rdata_i < reg2_rdata_i) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
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reg_wdata_o <= 32'h00000000;
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end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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if (reg1_rdata_i < reg2_rdata_i) begin
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reg_wdata_o <= 32'h00000001;
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end else begin
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reg_wdata_o <= 32'h00000000;
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end
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end
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end
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`INST_XOR: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i ^ reg2_rdata_i;
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end
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`INST_SR: begin
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jump_flag_o <= `JumpDisable;
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if (inst_i[30] == 1'b1) begin
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reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]);
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end else begin
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reg_wdata_o <= reg1_rdata_i >> reg2_rdata_i[4:0];
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end
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end
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`INST_OR: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i | reg2_rdata_i;
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end
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`INST_AND: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= reg1_rdata_i & reg2_rdata_i;
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end
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endcase
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end else if (funct7 == 7'b0000001) begin
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case (funct3)
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`INST_MUL: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= mul_temp[31:0];
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end
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`INST_MULHU: begin
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jump_flag_o <= `JumpDisable;
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reg_wdata_o <= mul_temp[63:32];
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end
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`INST_MULH: begin
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jump_flag_o <= `JumpDisable;
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if ((reg1_rdata_i[31] == 1'b0) && (reg2_rdata_i[31] == 1'b0)) begin
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reg_wdata_o <= mulh_temp[63:32];
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end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b1)) begin
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reg_wdata_o <= mulh_temp[63:32];
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end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b0)) begin
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reg_wdata_o <= mulh_temp_invert[63:32];
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end else begin
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reg_wdata_o <= mulh_temp_invert[63:32];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_MULHSU: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
if (reg1_rdata_i[31] == 1'b1) begin
|
||
|
|
reg_wdata_o <= mulhsu_temp_invert[63:32];
|
||
|
|
end else begin
|
||
|
|
reg_wdata_o <= mulhsu_temp[63:32];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_DIV: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
div_start_o <= `DivStart;
|
||
|
|
div_starting <= `DivStart;
|
||
|
|
div_rd_reg <= rd;
|
||
|
|
div_funct3 <= funct3;
|
||
|
|
hold_addr_o <= inst_addr_i + 4'h4;
|
||
|
|
end
|
||
|
|
`INST_DIVU: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
div_start_o <= `DivStart;
|
||
|
|
div_starting <= `DivStart;
|
||
|
|
div_rd_reg <= rd;
|
||
|
|
div_funct3 <= funct3;
|
||
|
|
hold_addr_o <= inst_addr_i + 4'h4;
|
||
|
|
end
|
||
|
|
`INST_REM: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
div_start_o <= `DivStart;
|
||
|
|
div_starting <= `DivStart;
|
||
|
|
div_rd_reg <= rd;
|
||
|
|
div_funct3 <= funct3;
|
||
|
|
hold_addr_o <= inst_addr_i + 4'h4;
|
||
|
|
end
|
||
|
|
`INST_REMU: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
div_start_o <= `DivStart;
|
||
|
|
div_starting <= `DivStart;
|
||
|
|
div_rd_reg <= rd;
|
||
|
|
div_funct3 <= funct3;
|
||
|
|
hold_addr_o <= inst_addr_i + 4'h4;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_TYPE_L: begin
|
||
|
|
case (funct3)
|
||
|
|
`INST_LB: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
||
|
|
if (sram_raddr_index == 2'b0)
|
||
|
|
reg_wdata_o <= {{24{sram_rdata_i[7]}}, sram_rdata_i[7:0]};
|
||
|
|
else if (sram_raddr_index == 2'b01)
|
||
|
|
reg_wdata_o <= {{24{sram_rdata_i[15]}}, sram_rdata_i[15:8]};
|
||
|
|
else if (sram_raddr_index == 2'b10)
|
||
|
|
reg_wdata_o <= {{24{sram_rdata_i[23]}}, sram_rdata_i[23:16]};
|
||
|
|
else
|
||
|
|
reg_wdata_o <= {{24{sram_rdata_i[31]}}, sram_rdata_i[31:24]};
|
||
|
|
end
|
||
|
|
`INST_LH: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
||
|
|
if (sram_raddr_index == 2'b0)
|
||
|
|
reg_wdata_o <= {{16{sram_rdata_i[15]}}, sram_rdata_i[15:0]};
|
||
|
|
else
|
||
|
|
reg_wdata_o <= {{16{sram_rdata_i[31]}}, sram_rdata_i[31:16]};
|
||
|
|
end
|
||
|
|
`INST_LW: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
||
|
|
reg_wdata_o <= sram_rdata_i;
|
||
|
|
end
|
||
|
|
`INST_LBU: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
||
|
|
if (sram_raddr_index == 2'b0)
|
||
|
|
reg_wdata_o <= {24'h0, sram_rdata_i[7:0]};
|
||
|
|
else if (sram_raddr_index == 2'b01)
|
||
|
|
reg_wdata_o <= {24'h0, sram_rdata_i[15:8]};
|
||
|
|
else if (sram_raddr_index == 2'b10)
|
||
|
|
reg_wdata_o <= {24'h0, sram_rdata_i[23:16]};
|
||
|
|
else
|
||
|
|
reg_wdata_o <= {24'h0, sram_rdata_i[31:24]};
|
||
|
|
end
|
||
|
|
`INST_LHU: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
||
|
|
if (sram_raddr_index == 2'b0)
|
||
|
|
reg_wdata_o <= {16'h0, sram_rdata_i[15:0]};
|
||
|
|
else
|
||
|
|
reg_wdata_o <= {16'h0, sram_rdata_i[31:16]};
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
`INST_TYPE_S: begin
|
||
|
|
case (funct3)
|
||
|
|
`INST_SB: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
||
|
|
sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
||
|
|
if (sram_waddr_index == 2'b00)
|
||
|
|
sram_wdata_o <= {sram_rdata_i[31:8], reg2_rdata_i[7:0]};
|
||
|
|
else if (sram_waddr_index == 2'b01)
|
||
|
|
sram_wdata_o <= {sram_rdata_i[31:16], reg2_rdata_i[7:0], sram_rdata_i[7:0]};
|
||
|
|
else if (sram_waddr_index == 2'b10)
|
||
|
|
sram_wdata_o <= {sram_rdata_i[31:24], reg2_rdata_i[7:0], sram_rdata_i[15:0]};
|
||
|
|
else
|
||
|
|
sram_wdata_o <= {reg2_rdata_i[7:0], sram_rdata_i[23:0]};
|
||
|
|
end
|
||
|
|
`INST_SH: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
||
|
|
sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
||
|
|
if (sram_waddr_index == 2'b00)
|
||
|
|
sram_wdata_o <= {sram_rdata_i[31:16], reg2_rdata_i[15:0]};
|
||
|
|
else
|
||
|
|
sram_wdata_o <= {reg2_rdata_i[15:0], sram_rdata_i[15:0]};
|
||
|
|
end
|
||
|
|
`INST_SW: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
||
|
|
sram_wdata_o <= reg2_rdata_i;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
`INST_TYPE_B: begin
|
||
|
|
case (funct3)
|
||
|
|
`INST_BEQ: begin
|
||
|
|
if (reg1_rdata_i == reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_BNE: begin
|
||
|
|
if (reg1_rdata_i != reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_BLT: begin
|
||
|
|
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
||
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
||
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_BGE: begin
|
||
|
|
if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
||
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
||
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_BLTU: begin
|
||
|
|
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
||
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
||
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end
|
||
|
|
`INST_BGEU: begin
|
||
|
|
if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
||
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
||
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end else begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||
|
|
end
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
`INST_JAL: begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
|
||
|
|
reg_wdata_o <= inst_addr_i + 4'h4;
|
||
|
|
end
|
||
|
|
`INST_JALR: begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe);
|
||
|
|
reg_wdata_o <= inst_addr_i + 4'h4;
|
||
|
|
end
|
||
|
|
`INST_LUI: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
reg_wdata_o <= {inst_i[31:12], 12'b0};
|
||
|
|
end
|
||
|
|
`INST_AUIPC: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
reg_wdata_o <= {inst_i[31:12], 12'b0} + inst_addr_i;
|
||
|
|
end
|
||
|
|
`INST_NOP: begin
|
||
|
|
jump_flag_o <= `JumpDisable;
|
||
|
|
end
|
||
|
|
`INST_FENCE: begin
|
||
|
|
jump_flag_o <= `JumpEnable;
|
||
|
|
jump_addr_o <= inst_addr_i + 4'h4;
|
||
|
|
end
|
||
|
|
default: begin
|
||
|
|
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|