52 lines
1.7 KiB
Systemverilog
52 lines
1.7 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 上升沿、下降沿检测
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module edge_detect (
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input logic clk_i,
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input logic rst_ni,
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input logic sig_i,
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output logic sig_o,
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output logic re_o,
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output logic fe_o
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);
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logic sig, sig_q;
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assign sig_o = sig_q;
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assign fe_o = (~sig) & sig_q;
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assign re_o = sig & (~sig_q);
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always_ff @(posedge clk_i, negedge rst_ni) begin
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if (!rst_ni) begin
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sig_q <= 1'b0;
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end else begin
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sig_q <= sig;
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end
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end
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gen_ticks_sync #(
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.DP(2),
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.DW(1)
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) u_sync (
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.clk(clk_i),
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.rst_n(rst_ni),
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.din(sig_i),
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.dout(sig)
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);
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endmodule
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