2019-12-04 00:47:19 +00:00
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/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// identify module
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module id (
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input wire clk,
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input wire rst,
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input wire[`SramBus] inst_i, // inst content
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input wire[`SramAddrBus] inst_addr_i, // inst addr
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input wire jump_flag_ex_i,
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// to regs
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output reg reg1_re_o, // reg1 read enable
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output reg[`RegAddrBus] reg1_raddr_o, // reg1 read addr
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output reg reg2_re_o, // reg2 read enable
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output reg[`RegAddrBus] reg2_raddr_o, // reg2 read addr
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output reg reg_we_o, // reg write enable
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output reg[`RegAddrBus] reg_waddr_o, // reg write addr
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// to ex
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output reg[`SramBus] inst_o,
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output reg inst_valid_o, // inst is valid flag
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output reg[`SramAddrBus] inst_addr_o,
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// to sram
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output reg sram_re_o, // ram read enable
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output reg sram_we_o // ram write enable
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);
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wire[6:0] opcode = inst_i[6:0];
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wire[2:0] funct3 = inst_i[14:12];
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2020-01-02 08:12:13 +00:00
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wire[6:0] funct7 = inst_i[31:25];
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2019-12-04 00:47:19 +00:00
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wire[4:0] rd = inst_i[11:7];
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wire[4:0] rs1 = inst_i[19:15];
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wire[4:0] rs2 = inst_i[24:20];
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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inst_o <= `ZeroWord;
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reg_we_o <= `WriteDisable;
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sram_we_o <= `WriteDisable;
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reg1_re_o <= `ReadDisable;
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reg2_re_o <= `ReadDisable;
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sram_re_o <= `ReadDisable;
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inst_valid_o <= `InstInvalid;
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end else if (jump_flag_ex_i == `JumpEnable && inst_i != `INST_NOP) begin
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inst_valid_o <= `InstValid;
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sram_we_o <= `WriteDisable;
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reg_we_o <= `WriteDisable;
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inst_o <= `INST_NOP;
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end else begin
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inst_o <= inst_i;
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inst_addr_o <= inst_addr_i;
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case (opcode)
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`INST_TYPE_I: begin
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case (funct3)
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`INST_ADDI: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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`INST_SLTI: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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`INST_SLTIU: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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`INST_XORI: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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`INST_ORI: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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`INST_ANDI: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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`INST_SLLI: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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`INST_SRI: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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sram_we_o <= `WriteDisable;
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end
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default: begin
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inst_valid_o <= `InstInvalid;
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end
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endcase
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end
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2020-01-02 08:12:13 +00:00
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`INST_TYPE_R_M: begin
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if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
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case (funct3)
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`INST_ADD_SUB: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_SLL: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_SLT: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_SLTU: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_XOR: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_SR: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_OR: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_AND: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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default: begin
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inst_valid_o <= `InstInvalid;
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end
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endcase
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end else if (funct7 == 7'b0000001) begin
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case (funct3)
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`INST_MUL: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_MULHU: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_MULH: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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`INST_MULHSU: begin
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inst_valid_o <= `InstValid;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg2_re_o <= `ReadEnable;
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reg2_raddr_o <= rs2;
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sram_we_o <= `WriteDisable;
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end
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default: begin
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inst_valid_o <= `InstInvalid;
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end
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endcase
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end
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2019-12-04 00:47:19 +00:00
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end
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`INST_TYPE_L: begin
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case (funct3)
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`INST_LB: begin
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inst_valid_o <= `InstValid;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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sram_re_o <= `ReadEnable;
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sram_we_o <= `WriteDisable;
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end
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`INST_LH: begin
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inst_valid_o <= `InstValid;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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sram_re_o <= `ReadEnable;
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sram_we_o <= `WriteDisable;
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end
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`INST_LW: begin
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inst_valid_o <= `InstValid;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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sram_re_o <= `ReadEnable;
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sram_we_o <= `WriteDisable;
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end
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`INST_LBU: begin
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inst_valid_o <= `InstValid;
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reg1_re_o <= `ReadEnable;
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reg1_raddr_o <= rs1;
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reg_we_o <= `WriteEnable;
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reg_waddr_o <= rd;
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sram_re_o <= `ReadEnable;
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sram_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_LHU: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg_we_o <= `WriteEnable;
|
|
|
|
|
reg_waddr_o <= rd;
|
|
|
|
|
sram_re_o <= `ReadEnable;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
inst_valid_o <= `InstInvalid;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_TYPE_S: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_SB: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteEnable;
|
|
|
|
|
sram_re_o <= `ReadEnable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_SH: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteEnable;
|
|
|
|
|
sram_re_o <= `ReadEnable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_SW: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteEnable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
inst_valid_o <= `InstInvalid;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_TYPE_B: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_BEQ: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_BNE: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_BLT: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_BGE: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_BLTU: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_BGEU: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg2_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg2_raddr_o <= rs2;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
inst_valid_o <= `InstInvalid;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_JAL: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteEnable;
|
|
|
|
|
reg_waddr_o <= rd;
|
|
|
|
|
end
|
|
|
|
|
`INST_JALR: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteEnable;
|
|
|
|
|
reg1_re_o <= `ReadEnable;
|
|
|
|
|
reg1_raddr_o <= rs1;
|
|
|
|
|
reg_waddr_o <= rd;
|
|
|
|
|
end
|
|
|
|
|
`INST_LUI: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteEnable;
|
|
|
|
|
reg_waddr_o <= rd;
|
|
|
|
|
end
|
|
|
|
|
`INST_AUIPC: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteEnable;
|
|
|
|
|
reg_waddr_o <= rd;
|
|
|
|
|
end
|
|
|
|
|
`INST_NOP: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
`INST_FENCE: begin
|
|
|
|
|
inst_valid_o <= `InstValid;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
inst_valid_o <= `InstInvalid;
|
|
|
|
|
sram_we_o <= `WriteDisable;
|
|
|
|
|
reg_we_o <= `WriteDisable;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
endmodule
|
