29 lines
612 B
Systemverilog
29 lines
612 B
Systemverilog
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register slice conforming to Comportibility guide.
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module prim_subreg_ext #(
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parameter int unsigned DW = 32
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) (
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input re,
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input we,
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input [DW-1:0] wd,
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input [DW-1:0] d,
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// output to HW and Reg Read
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output logic qe,
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output logic qre,
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output logic [DW-1:0] q,
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output logic [DW-1:0] qs
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);
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assign qs = d;
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assign q = wd;
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assign qe = we;
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assign qre = re;
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endmodule
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