103 lines
3.3 KiB
Systemverilog
103 lines
3.3 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module timer_core (
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input logic clk_i,
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input logic rst_ni,
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output logic irq_o,
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input logic reg_we_i,
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input logic reg_re_i,
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input logic [31:0] reg_wdata_i,
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input logic [ 3:0] reg_be_i,
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input logic [31:0] reg_addr_i,
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output logic [31:0] reg_rdata_o
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);
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import timer_reg_pkg::*;
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timer_reg_pkg::timer_reg2hw_t reg2hw;
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timer_reg_pkg::timer_hw2reg_t hw2reg;
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logic start;
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logic int_en;
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logic int_pending;
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logic mode;
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logic [23:0] div_cont;
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logic [31:0] count_q;
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logic [31:0] value;
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logic tick;
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assign start = reg2hw.ctrl.en.q;
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assign int_en = reg2hw.ctrl.int_en.q;
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assign int_pending = reg2hw.ctrl.int_pending.q;
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assign mode = reg2hw.ctrl.mode.q;
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assign div_cont = reg2hw.ctrl.clk_div.q;
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assign value = reg2hw.value.q;
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// 当前计数值
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assign hw2reg.count.d = count_q;
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assign hw2reg.ctrl.int_pending.d = 1'b1;
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assign hw2reg.ctrl.int_pending.de = (count_q == value) && int_en && start;
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assign hw2reg.ctrl.en.d = 1'b0;
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assign hw2reg.ctrl.en.de = (count_q == value) && (mode == 1'b0) && start;
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assign irq_o = int_pending;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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count_q <= 32'h0;
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end else begin
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if (start) begin
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if (tick) begin
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count_q <= count_q + 1'b1;
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if (count_q == value) begin
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count_q <= 32'h0;
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end
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end
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end else begin
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count_q <= 32'h0;
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end
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end
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end
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clk_div #(
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.RATIO_WIDTH(24)
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) u_clk_div (
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.clk_i(clk_i),
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.rst_ni(rst_ni || (~(count_q == value))),
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.en_i(start),
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.ratio_i(div_cont),
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.clk_o(tick)
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);
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timer_reg_top u_timer_reg_top (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.reg2hw (reg2hw),
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.hw2reg (hw2reg),
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.reg_we (reg_we_i),
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.reg_re (reg_re_i),
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.reg_wdata (reg_wdata_i),
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.reg_be (reg_be_i),
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.reg_addr (reg_addr_i),
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.reg_rdata (reg_rdata_o)
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);
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endmodule
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