49 lines
1.6 KiB
Systemverilog
49 lines
1.6 KiB
Systemverilog
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// Copyright 2018 Robert Balas <balasr@student.ethz.ch>
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// Top level wrapper for a verilator RI5CY testbench
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// Contributor: Robert Balas <balasr@student.ethz.ch>
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module tb_top_verilator #(
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) (
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input clk_i,
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input rst_ni,
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input fetch_enable_i
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);
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initial begin: load_prog
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automatic logic [1023:0] firmware;
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if($value$plusargs("firmware=%s", firmware)) begin
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//if($test$plusargs("verbose"))
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$display("[TESTBENCH] %t: loading firmware %0s ...",
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$time, firmware);
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$readmemh (firmware, u_tinyriscv_soc_top.u_rom.u_gen_ram.ram);
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//$display("mem[0x80]=0x%x", u_ram.ram.mem[32]);
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//$display("mem[0x84]=0x%x", u_ram.ram.mem[33]);
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end else begin
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$display("No firmware specified");
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end
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end
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tinyriscv_soc_top u_tinyriscv_soc_top(
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.clk(clk_i),
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.rst_ext_i(rst_ni)
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);
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endmodule // tb_top_verilator
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