2019-12-04 00:47:19 +00:00
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/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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2020-02-22 07:24:10 +00:00
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// execute and writeback module
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2020-03-29 15:19:14 +00:00
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module ex(
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2019-12-04 00:47:19 +00:00
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input wire rst,
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// from id
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2020-03-29 15:19:14 +00:00
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input wire[`InstBus] inst_i, // inst content
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input wire[`InstAddrBus] inst_addr_i, // inst addr
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2020-01-13 00:26:41 +00:00
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input wire reg_we_i,
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input wire[`RegAddrBus] reg_waddr_i,
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2019-12-04 00:47:19 +00:00
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input wire[`RegBus] reg1_rdata_i, // reg1 read data
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input wire[`RegBus] reg2_rdata_i, // reg2 read data
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2020-04-05 14:22:34 +00:00
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input wire csr_we_i,
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input wire[`MemAddrBus] csr_waddr_i,
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input wire[`RegBus] csr_rdata_i,
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2020-04-11 11:03:49 +00:00
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input wire int_assert_i,
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input wire[`InstAddrBus] int_addr_i,
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2019-12-04 00:47:19 +00:00
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2020-03-29 15:19:14 +00:00
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// from mem
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input wire[`MemBus] mem_rdata_i, // mem read data
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2019-12-04 00:47:19 +00:00
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2020-01-13 00:26:41 +00:00
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// from div
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input wire div_ready_i,
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input wire[`DoubleRegBus] div_result_i,
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2020-03-29 15:19:14 +00:00
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input wire div_busy_i,
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input wire[2:0] div_op_i,
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input wire[`RegAddrBus] div_reg_waddr_i,
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// to mem
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output reg[`MemBus] mem_wdata_o, // mem write data
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output reg[`MemAddrBus] mem_raddr_o, // mem read addr
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output reg[`MemAddrBus] mem_waddr_o, // mem write addr
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2020-04-11 11:03:49 +00:00
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output wire mem_we_o, // mem write enable
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output wire mem_req_o,
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2019-12-04 00:47:19 +00:00
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// to regs
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2020-03-29 15:19:14 +00:00
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output wire[`RegBus] reg_wdata_o, // reg write data
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output wire reg_we_o, // reg write enable
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output wire[`RegAddrBus] reg_waddr_o, // reg write addr
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2020-01-13 00:26:41 +00:00
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2020-04-05 14:22:34 +00:00
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// to csr reg
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output reg[`RegBus] csr_wdata_o, // reg write data
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output wire csr_we_o, // reg write enable
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output wire[`MemAddrBus] csr_waddr_o,
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2020-01-13 00:26:41 +00:00
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// to div
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output reg div_start_o,
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2020-03-29 15:19:14 +00:00
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output reg[`RegBus] div_dividend_o,
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output reg[`RegBus] div_divisor_o,
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output reg[2:0] div_op_o,
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output reg[`RegAddrBus] div_reg_waddr_o,
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2020-01-13 00:26:41 +00:00
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2020-03-29 15:19:14 +00:00
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// to ctrl
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output wire hold_flag_o,
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output wire jump_flag_o, // whether jump or not flag
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output wire[`InstAddrBus] jump_addr_o // jump dest addr
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2019-12-04 00:47:19 +00:00
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2020-02-23 09:01:45 +00:00
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);
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2019-12-04 00:47:19 +00:00
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wire[31:0] sign_extend_tmp;
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wire[4:0] shift_bits;
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2020-03-29 15:19:14 +00:00
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wire[1:0] mem_raddr_index;
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wire[1:0] mem_waddr_index;
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2020-01-02 08:12:13 +00:00
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wire[`DoubleRegBus] mul_temp;
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2020-03-29 15:19:14 +00:00
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wire[`DoubleRegBus] mul_temp_invert;
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reg[`RegBus] mul_op1;
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reg[`RegBus] mul_op2;
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2020-02-22 07:24:10 +00:00
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wire[6:0] opcode;
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wire[2:0] funct3;
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wire[6:0] funct7;
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wire[4:0] rd;
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2020-04-05 14:22:34 +00:00
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wire[4:0] uimm;
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2020-03-29 15:19:14 +00:00
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reg[`RegBus] reg_wdata;
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reg reg_we;
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reg[`RegAddrBus] reg_waddr;
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reg[`RegBus] div_wdata;
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reg div_we;
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reg[`RegAddrBus] div_waddr;
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reg div_hold_flag;
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reg div_jump_flag;
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reg[`InstAddrBus] div_jump_addr;
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reg hold_flag;
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reg jump_flag;
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reg[`InstAddrBus] jump_addr;
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2020-04-11 11:03:49 +00:00
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reg mem_we;
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reg mem_req;
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2019-12-04 00:47:19 +00:00
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2020-02-22 07:24:10 +00:00
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assign opcode = inst_i[6:0];
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assign funct3 = inst_i[14:12];
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assign funct7 = inst_i[31:25];
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assign rd = inst_i[11:7];
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2020-04-05 14:22:34 +00:00
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assign uimm = inst_i[19:15];
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2019-12-04 00:47:19 +00:00
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assign sign_extend_tmp = {{20{inst_i[31]}}, inst_i[31:20]};
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assign shift_bits = inst_i[24:20];
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2020-01-02 08:12:13 +00:00
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2020-03-29 15:19:14 +00:00
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assign mul_temp = mul_op1 * mul_op2;
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assign mul_temp_invert = ~mul_temp + 1;
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assign mem_raddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11;
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assign mem_waddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11;
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2020-02-16 13:27:11 +00:00
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2020-03-29 15:19:14 +00:00
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assign reg_wdata_o = reg_wdata | div_wdata;
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2020-04-11 11:03:49 +00:00
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assign reg_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: (reg_we || div_we);
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2020-03-29 15:19:14 +00:00
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assign reg_waddr_o = reg_waddr | div_waddr;
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2019-12-04 00:47:19 +00:00
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2020-04-11 11:03:49 +00:00
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assign mem_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: mem_we;
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assign mem_req_o = (int_assert_i == `INT_ASSERT)? `RIB_NREQ: mem_req;
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2020-03-29 15:19:14 +00:00
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assign hold_flag_o = hold_flag || div_hold_flag;
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2020-04-11 11:03:49 +00:00
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assign jump_flag_o = jump_flag || div_jump_flag || ((int_assert_i == `INT_ASSERT)? `JumpEnable: `JumpDisable);
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assign jump_addr_o = (int_assert_i == `INT_ASSERT)? int_addr_i: (jump_addr | div_jump_addr);
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2020-01-13 00:26:41 +00:00
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2020-04-11 11:03:49 +00:00
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assign csr_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: csr_we_i;
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2020-04-05 14:22:34 +00:00
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assign csr_waddr_o = csr_waddr_i;
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2020-03-29 15:19:14 +00:00
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// handle mul
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always @ (*) begin
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if (rst == `RstEnable) begin
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mul_op1 <= `ZeroWord;
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mul_op2 <= `ZeroWord;
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end else begin
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if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin
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2020-04-18 03:23:46 +00:00
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case (funct3)
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`INST_MUL: begin
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mul_op1 <= reg1_rdata_i;
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mul_op2 <= reg2_rdata_i;
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end
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`INST_MULHU: begin
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mul_op1 <= reg1_rdata_i;
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mul_op2 <= reg2_rdata_i;
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end
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`INST_MULHSU: begin
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mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
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mul_op2 <= reg2_rdata_i;
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end
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`INST_MULH: begin
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mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
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mul_op2 <= (reg2_rdata_i[31] == 1'b1)? (~reg2_rdata_i + 1): reg2_rdata_i;
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end
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default: begin
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mul_op1 <= reg1_rdata_i;
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mul_op2 <= reg2_rdata_i;
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end
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endcase
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2020-03-29 15:19:14 +00:00
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end else begin
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mul_op1 <= reg1_rdata_i;
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mul_op2 <= reg2_rdata_i;
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2020-03-08 07:09:30 +00:00
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end
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end
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end
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2020-03-29 15:19:14 +00:00
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// handle div
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2020-01-13 00:26:41 +00:00
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always @ (*) begin
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2020-02-22 07:24:10 +00:00
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if (rst == `RstEnable) begin
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2020-03-29 15:19:14 +00:00
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div_dividend_o <= `ZeroWord;
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div_divisor_o <= `ZeroWord;
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div_op_o <= 3'b0;
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div_reg_waddr_o <= `ZeroWord;
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div_waddr <= `ZeroWord;
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div_hold_flag <= `HoldDisable;
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div_we <= `WriteDisable;
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div_wdata <= `ZeroWord;
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2020-02-22 07:24:10 +00:00
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div_start_o <= `DivStop;
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2020-03-29 15:19:14 +00:00
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div_jump_flag <= `JumpDisable;
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div_jump_addr <= `ZeroWord;
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end else begin
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div_dividend_o <= reg1_rdata_i;
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div_divisor_o <= reg2_rdata_i;
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div_op_o <= funct3;
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div_reg_waddr_o <= reg_waddr_i;
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if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin
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div_we <= `WriteDisable;
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div_wdata <= `ZeroWord;
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div_waddr <= `ZeroWord;
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case (funct3)
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`INST_DIV: begin
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div_start_o <= `DivStart;
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div_jump_flag <= `JumpEnable;
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div_hold_flag <= `HoldEnable;
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div_jump_addr <= inst_addr_i + 4'h4;
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end
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`INST_DIVU: begin
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div_start_o <= `DivStart;
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div_jump_flag <= `JumpEnable;
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div_hold_flag <= `HoldEnable;
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div_jump_addr <= inst_addr_i + 4'h4;
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end
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`INST_REM: begin
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div_start_o <= `DivStart;
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div_jump_flag <= `JumpEnable;
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div_hold_flag <= `HoldEnable;
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div_jump_addr <= inst_addr_i + 4'h4;
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end
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`INST_REMU: begin
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div_start_o <= `DivStart;
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div_jump_flag <= `JumpEnable;
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div_hold_flag <= `HoldEnable;
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div_jump_addr <= inst_addr_i + 4'h4;
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end
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default: begin
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div_start_o <= `DivStop;
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div_jump_flag <= `JumpDisable;
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div_hold_flag <= `HoldDisable;
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div_jump_addr <= `ZeroWord;
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end
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endcase
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end else begin
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div_jump_flag <= `JumpDisable;
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div_jump_addr <= `ZeroWord;
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if (div_busy_i == `True) begin
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div_start_o <= `DivStart;
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div_we <= `WriteDisable;
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div_wdata <= `ZeroWord;
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div_waddr <= `ZeroWord;
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div_hold_flag <= `HoldEnable;
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end else begin
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div_start_o <= `DivStop;
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div_hold_flag <= `HoldDisable;
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if (div_ready_i == `DivResultReady) begin
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case (div_op_i)
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`INST_DIV: begin
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div_wdata <= div_result_i[31:0];
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div_waddr <= div_reg_waddr_i;
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div_we <= `WriteEnable;
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end
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`INST_DIVU: begin
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div_wdata <= div_result_i[31:0];
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div_waddr <= div_reg_waddr_i;
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div_we <= `WriteEnable;
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end
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`INST_REM: begin
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div_wdata <= div_result_i[63:32];
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div_waddr <= div_reg_waddr_i;
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div_we <= `WriteEnable;
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end
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`INST_REMU: begin
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div_wdata <= div_result_i[63:32];
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div_waddr <= div_reg_waddr_i;
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div_we <= `WriteEnable;
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end
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default: begin
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div_wdata <= `ZeroWord;
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div_waddr <= `ZeroWord;
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div_we <= `WriteDisable;
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end
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endcase
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end else begin
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div_we <= `WriteDisable;
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div_wdata <= `ZeroWord;
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div_waddr <= `ZeroWord;
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end
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end
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end
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end
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end
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|
|
|
|
|
|
|
always @ (*) begin
|
|
|
|
|
if (rst == `RstEnable) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
|
|
|
|
mem_req <= `RIB_NREQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
reg_we <= `WriteDisable;
|
|
|
|
|
reg_waddr <= `ZeroWord;
|
2020-04-05 14:22:34 +00:00
|
|
|
csr_wdata_o <= `ZeroWord;
|
2020-02-22 07:24:10 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_we <= reg_we_i;
|
|
|
|
|
reg_waddr <= reg_waddr_i;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_req <= `RIB_NREQ;
|
2020-04-05 14:22:34 +00:00
|
|
|
csr_wdata_o <= `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
|
|
|
|
|
case (opcode)
|
|
|
|
|
`INST_TYPE_I: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_ADDI: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SLTI: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i < sign_extend_tmp) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
|
|
|
|
end
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
|
|
|
|
end else begin
|
|
|
|
|
if (reg1_rdata_i < sign_extend_tmp) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
|
|
|
|
end
|
|
|
|
|
end
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SLTIU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i < sign_extend_tmp) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
|
|
|
|
end
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
|
|
|
|
end else begin
|
|
|
|
|
if (reg1_rdata_i < sign_extend_tmp) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_XORI: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
end
|
|
|
|
|
`INST_ORI: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
end
|
|
|
|
|
`INST_ANDI: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
end
|
|
|
|
|
`INST_SLLI: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i << shift_bits;
|
|
|
|
|
end
|
|
|
|
|
`INST_SRI: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (inst_i[30] == 1'b1) begin
|
|
|
|
|
reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits);
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= reg1_rdata_i >> shift_bits;
|
|
|
|
|
end
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_TYPE_R_M: begin
|
|
|
|
|
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
|
2020-01-02 08:12:13 +00:00
|
|
|
case (funct3)
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_ADD_SUB: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (inst_i[30] == 1'b0) begin
|
|
|
|
|
reg_wdata <= reg1_rdata_i + reg2_rdata_i;
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= reg1_rdata_i - reg2_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_SLL: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i << reg2_rdata_i[4:0];
|
|
|
|
|
end
|
|
|
|
|
`INST_SLT: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
2020-01-02 08:12:13 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= 32'h00000000;
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
2020-01-02 08:12:13 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
2020-01-02 08:12:13 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= 32'h00000000;
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SLTU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
2020-01-02 08:12:13 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= 32'h00000000;
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
reg_wdata <= 32'h00000000;
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
reg_wdata <= 32'h00000001;
|
2020-01-02 08:12:13 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= 32'h00000000;
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
|
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_XOR: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i ^ reg2_rdata_i;
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SR: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-02-22 07:24:10 +00:00
|
|
|
if (inst_i[30] == 1'b1) begin
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]);
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i >> reg2_rdata_i[4:0];
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
|
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_OR: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i | reg2_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_AND: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= reg1_rdata_i & reg2_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
2020-02-22 07:24:10 +00:00
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (funct7 == 7'b0000001) begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_MUL: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= mul_temp[31:0];
|
|
|
|
|
end
|
|
|
|
|
`INST_MULHU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= mul_temp[63:32];
|
|
|
|
|
end
|
|
|
|
|
`INST_MULH: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if ((reg1_rdata_i[31] == 1'b0) && (reg2_rdata_i[31] == 1'b0)) begin
|
|
|
|
|
reg_wdata <= mul_temp[63:32];
|
|
|
|
|
end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b1)) begin
|
|
|
|
|
reg_wdata <= mul_temp[63:32];
|
|
|
|
|
end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b0)) begin
|
|
|
|
|
reg_wdata <= mul_temp_invert[63:32];
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= mul_temp_invert[63:32];
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_MULHSU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i[31] == 1'b1) begin
|
|
|
|
|
reg_wdata <= mul_temp_invert[63:32];
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= mul_temp[63:32];
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end/*
|
|
|
|
|
`INST_DIV: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
2020-01-13 00:26:41 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_DIVU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
`INST_REM: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
`INST_REMU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end*/
|
|
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_TYPE_L: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_LB: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
|
|
|
|
//mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
if (mem_raddr_index == 2'b0) begin
|
|
|
|
|
reg_wdata <= {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]};
|
|
|
|
|
end else if (mem_raddr_index == 2'b01) begin
|
|
|
|
|
reg_wdata <= {{24{mem_rdata_i[15]}}, mem_rdata_i[15:8]};
|
|
|
|
|
end else if (mem_raddr_index == 2'b10) begin
|
|
|
|
|
reg_wdata <= {{24{mem_rdata_i[23]}}, mem_rdata_i[23:16]};
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= {{24{mem_rdata_i[31]}}, mem_rdata_i[31:24]};
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_LH: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
|
|
|
|
//mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
if (mem_raddr_index == 2'b0) begin
|
|
|
|
|
reg_wdata <= {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]};
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= {{16{mem_rdata_i[31]}}, mem_rdata_i[31:16]};
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_LW: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
|
|
|
|
//mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
reg_wdata <= mem_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_LBU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
|
|
|
|
//mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
if (mem_raddr_index == 2'b0) begin
|
|
|
|
|
reg_wdata <= {24'h0, mem_rdata_i[7:0]};
|
|
|
|
|
end else if (mem_raddr_index == 2'b01) begin
|
|
|
|
|
reg_wdata <= {24'h0, mem_rdata_i[15:8]};
|
|
|
|
|
end else if (mem_raddr_index == 2'b10) begin
|
|
|
|
|
reg_wdata <= {24'h0, mem_rdata_i[23:16]};
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= {24'h0, mem_rdata_i[31:24]};
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_LHU: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
|
|
|
|
//mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
|
|
|
|
|
if (mem_raddr_index == 2'b0) begin
|
|
|
|
|
reg_wdata <= {16'h0, mem_rdata_i[15:0]};
|
|
|
|
|
end else begin
|
|
|
|
|
reg_wdata <= {16'h0, mem_rdata_i[31:16]};
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_TYPE_S: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_SB: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
reg_wdata <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteEnable;
|
|
|
|
|
mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
|
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
|
|
|
|
if (mem_waddr_index == 2'b00) begin
|
|
|
|
|
mem_wdata_o <= {mem_rdata_i[31:8], reg2_rdata_i[7:0]};
|
|
|
|
|
end else if (mem_waddr_index == 2'b01) begin
|
|
|
|
|
mem_wdata_o <= {mem_rdata_i[31:16], reg2_rdata_i[7:0], mem_rdata_i[7:0]};
|
|
|
|
|
end else if (mem_waddr_index == 2'b10) begin
|
|
|
|
|
mem_wdata_o <= {mem_rdata_i[31:24], reg2_rdata_i[7:0], mem_rdata_i[15:0]};
|
|
|
|
|
end else begin
|
|
|
|
|
mem_wdata_o <= {reg2_rdata_i[7:0], mem_rdata_i[23:0]};
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_SH: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
reg_wdata <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteEnable;
|
|
|
|
|
mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
|
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
|
|
|
|
if (mem_waddr_index == 2'b00) begin
|
|
|
|
|
mem_wdata_o <= {mem_rdata_i[31:16], reg2_rdata_i[15:0]};
|
|
|
|
|
end else begin
|
|
|
|
|
mem_wdata_o <= {reg2_rdata_i[15:0], mem_rdata_i[15:0]};
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_SW: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
reg_wdata <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteEnable;
|
|
|
|
|
mem_req <= `RIB_REQ;
|
2020-03-29 15:19:14 +00:00
|
|
|
mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
|
|
|
|
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
|
|
|
|
|
mem_wdata_o <= reg2_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_TYPE_B: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_BEQ: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
if (reg1_rdata_i == reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
|
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_BNE: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
if (reg1_rdata_i != reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
|
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_BLT: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BGE: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2020-02-22 07:24:10 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BLTU: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
if (reg1_rdata_i >= reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
|
|
|
|
end
|
|
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BGEU: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
|
|
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
|
|
|
|
|
if (reg1_rdata_i < reg2_rdata_i) begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
|
|
|
|
end
|
|
|
|
|
end else begin
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_JAL: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
|
|
|
|
|
reg_wdata <= inst_addr_i + 4'h4;
|
|
|
|
|
end
|
|
|
|
|
`INST_JALR: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe);
|
|
|
|
|
reg_wdata <= inst_addr_i + 4'h4;
|
|
|
|
|
end
|
|
|
|
|
`INST_LUI: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
reg_wdata <= {inst_i[31:12], 12'b0};
|
|
|
|
|
end
|
|
|
|
|
`INST_AUIPC: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
reg_wdata <= {inst_i[31:12], 12'b0} + inst_addr_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_NOP: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
`INST_FENCE: begin
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
jump_flag <= `JumpEnable;
|
|
|
|
|
jump_addr <= inst_addr_i + 4'h4;
|
|
|
|
|
end
|
2020-04-05 14:22:34 +00:00
|
|
|
`INST_CSR: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-04-05 14:22:34 +00:00
|
|
|
case (funct3)
|
|
|
|
|
`INST_CSRRW: begin
|
|
|
|
|
csr_wdata_o <= reg1_rdata_i;
|
|
|
|
|
reg_wdata <= csr_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_CSRRS: begin
|
|
|
|
|
csr_wdata_o <= reg1_rdata_i | csr_rdata_i;
|
|
|
|
|
reg_wdata <= csr_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_CSRRC: begin
|
|
|
|
|
csr_wdata_o <= csr_rdata_i & (~reg1_rdata_i);
|
|
|
|
|
reg_wdata <= csr_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_CSRRWI: begin
|
|
|
|
|
csr_wdata_o <= {27'h0, uimm};
|
|
|
|
|
reg_wdata <= csr_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_CSRRSI: begin
|
|
|
|
|
csr_wdata_o <= {27'h0, uimm} | csr_rdata_i;
|
|
|
|
|
reg_wdata <= csr_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
`INST_CSRRCI: begin
|
|
|
|
|
csr_wdata_o <= (~{27'h0, uimm}) & csr_rdata_i;
|
|
|
|
|
reg_wdata <= csr_rdata_i;
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-04-05 14:22:34 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
default: begin
|
|
|
|
|
jump_flag <= `JumpDisable;
|
|
|
|
|
hold_flag <= `HoldDisable;
|
|
|
|
|
jump_addr <= `ZeroWord;
|
|
|
|
|
mem_wdata_o <= `ZeroWord;
|
|
|
|
|
mem_raddr_o <= `ZeroWord;
|
|
|
|
|
mem_waddr_o <= `ZeroWord;
|
2020-04-11 11:03:49 +00:00
|
|
|
mem_we <= `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
reg_wdata <= `ZeroWord;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
endmodule
|
