86 lines
2.4 KiB
Systemverilog
86 lines
2.4 KiB
Systemverilog
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// See LICENSE.SiFive for license details.
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//VCS coverage exclude_file
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import "DPI-C" function int jtag_tick
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(
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input int port,
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output bit jtag_TCK,
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output bit jtag_TMS,
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output bit jtag_TDI,
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output bit jtag_TRSTn,
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input bit jtag_TDO
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);
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module sim_jtag #(
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parameter TICK_DELAY = 50,
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parameter PORT = 0
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)(
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input clock,
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input reset,
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input enable,
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input init_done,
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output jtag_TCK,
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output jtag_TMS,
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output jtag_TDI,
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output jtag_TRSTn,
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input jtag_TDO_data,
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input jtag_TDO_driven,
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output [31:0] exit
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);
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reg [31:0] tickCounterReg;
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wire [31:0] tickCounterNxt;
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assign tickCounterNxt = (tickCounterReg == 0) ? TICK_DELAY : (tickCounterReg - 1);
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bit r_reset;
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wire [31:0] random_bits = $random;
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wire #0.1 __jtag_TDO = jtag_TDO_driven ?
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jtag_TDO_data : random_bits[0];
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bit __jtag_TCK;
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bit __jtag_TMS;
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bit __jtag_TDI;
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bit __jtag_TRSTn;
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int __exit;
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reg init_done_sticky;
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assign #0.1 jtag_TCK = __jtag_TCK;
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assign #0.1 jtag_TMS = __jtag_TMS;
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assign #0.1 jtag_TDI = __jtag_TDI;
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assign #0.1 jtag_TRSTn = __jtag_TRSTn;
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assign #0.1 exit = __exit;
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always @(posedge clock) begin
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r_reset <= reset;
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if (reset || r_reset) begin
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__exit = 0;
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tickCounterReg <= TICK_DELAY;
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init_done_sticky <= 1'b0;
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end else begin
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init_done_sticky <= init_done | init_done_sticky;
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if (enable && init_done_sticky) begin
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tickCounterReg <= tickCounterNxt;
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if (tickCounterReg == 0) begin
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__exit = jtag_tick(PORT,
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__jtag_TCK,
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__jtag_TMS,
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__jtag_TDI,
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__jtag_TRSTn,
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__jtag_TDO);
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end
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end // if (enable && init_done_sticky)
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end // else: !if(reset || r_reset)
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end // always @ (posedge clock)
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endmodule
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