66 lines
2.2 KiB
Coq
66 lines
2.2 KiB
Coq
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/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// 流水线控制模块
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// 发出暂停、冲刷流水线信号
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module pipe_ctrl(
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input wire clk,
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input wire rst_n,
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input wire stall_from_id_i,
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input wire stall_from_ex_i,
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input wire stall_from_jtag_i,
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input wire stall_from_clint_i,
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input wire jump_assert_i,
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input wire[31:0] jump_addr_i,
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output wire flush_o,
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output wire[`STALL_WIDTH-1:0] stall_o,
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output wire[31:0] flush_addr_o
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);
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assign flush_addr_o = jump_addr_i;
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assign flush_o = jump_assert_i | stall_from_clint_i;
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reg[`STALL_WIDTH-1:0] stall;
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always @ (*) begin
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if (stall_from_ex_i | stall_from_clint_i) begin
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stall[`STALL_EX] = 1'b1;
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stall[`STALL_ID] = 1'b1;
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stall[`STALL_IF] = 1'b1;
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stall[`STALL_PC] = 1'b1;
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end else if (stall_from_id_i) begin
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stall[`STALL_EX] = 1'b0;
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stall[`STALL_ID] = 1'b0;
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stall[`STALL_IF] = 1'b1;
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stall[`STALL_PC] = 1'b1;
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end else begin
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stall[`STALL_EX] = 1'b0;
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stall[`STALL_ID] = 1'b0;
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stall[`STALL_IF] = 1'b0;
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stall[`STALL_PC] = 1'b0;
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end
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end
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assign stall_o = stall;
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endmodule
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