2021-03-31 07:25:22 +00:00
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PROG := ../sdk/examples/simple/simple.mem
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PROG_DIR := $(shell dirname $(PROG))
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MAKE := make
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VERILATOR := verilator
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VERI_FLAGS += +vcd
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2022-01-05 09:30:29 +00:00
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VERI_CFLAGS += -DVL_DEBUG
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2021-03-31 07:25:22 +00:00
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VERI_VFLAGS += -DTRACE_ENABLED
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RTL_FILES = ../rtl.flist
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VERI_OBJ_DIR := cobj_dir
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ifeq ($(findstring +vcd,$(VERI_FLAGS)),+vcd)
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VERI_TRACE = "--trace"
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VERI_CFLAGS += "-DVCD_TRACE"
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else
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VERI_TRACE =
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endif
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2021-05-14 06:37:47 +00:00
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SIM_SRC := sim_jtag.sv sim_ctrl.sv
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2021-03-31 07:25:22 +00:00
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SIM_SRC += tb_top_verilator.sv \
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tb_top_verilator.cpp
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SIM_TOP_MODULE := tb_top_verilator
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.DEFAULT_GOAL := sim
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all: sim
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.PHONY: recompile
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recompile:
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rm -rf $(VERI_OBJ_DIR) testbench_verilator
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$(MAKE) -C ./remote_bitbang clean
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$(MAKE) -C $(PROG_DIR) clean
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$(MAKE) compile
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.PHONY: compile
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compile: remote_bitbang/librbs.so $(PROG) testbench_verilator
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testbench_verilator:
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$(VERILATOR) --cc --sv --exe \
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$(VERI_TRACE) \
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--Wno-lint --Wno-UNOPTFLAT \
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--Wno-MODDUP --top-module \
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$(SIM_TOP_MODULE) \
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-f $(RTL_FILES) \
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$(SIM_SRC) \
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--Mdir $(VERI_OBJ_DIR) \
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$(VERI_VFLAGS) \
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-LDFLAGS "-L../remote_bitbang \
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-Wl,--enable-new-dtags -Wl,-rpath,remote_bitbang -lrbs" \
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-CFLAGS "-std=gnu++11 $(VERI_CFLAGS)"
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$(MAKE) -C $(VERI_OBJ_DIR) -f V$(SIM_TOP_MODULE).mk
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cp $(VERI_OBJ_DIR)/V$(SIM_TOP_MODULE) testbench_verilator
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remote_bitbang/librbs.so:
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$(MAKE) -C ./remote_bitbang all
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$(PROG):
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$(MAKE) -C $(PROG_DIR)
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.PHONY: run
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run:
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./testbench_verilator "+firmware=$(PROG)"
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.PHONY: sim
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sim: recompile run
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.PHONY: clean
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clean:
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rm -rf $(VERI_OBJ_DIR) testbench_verilator *.log *.vcd
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$(MAKE) -C ./remote_bitbang clean
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$(MAKE) -C $(PROG_DIR) clean
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.PHONY: help
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help:
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@echo 'rebuild all:'
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@echo 'make PROG=/path/file.mem recompile'
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@echo 'run directly:'
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@echo 'make PROG=/path/file.mem run'
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@echo 'rebuild & run:'
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@echo 'make PROG=/path/file.mem sim'
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@echo 'clean obj files:'
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@echo 'make PROG=/path/file.mem clean'
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