tinyriscv/tests/isa/generated/rv32ui-p-andi.verilog

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@00000000
13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0
13 FF F0 F0 B7 0E 01 FF 93 8E 0E F0 93 01 20 00
63 14 DF 1B B7 10 F0 0F 93 80 00 FF 13 FF 00 0F
93 0E 00 0F 93 01 30 00 63 18 DF 19 B7 00 FF 00
93 80 F0 0F 13 FF F0 70 93 0E F0 00 93 01 40 00
63 1C DF 17 B7 F0 0F F0 93 80 F0 00 13 FF 00 0F
93 0E 00 00 93 01 50 00 63 10 DF 17 B7 00 01 FF
93 80 00 F0 93 F0 00 0F 93 0E 00 00 93 01 60 00
63 94 D0 15 13 02 00 00 B7 10 F0 0F 93 80 00 FF
13 FF F0 70 13 03 0F 00 13 02 12 00 93 02 20 00
E3 14 52 FE 93 0E 00 70 93 01 70 00 63 1E D3 11
13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 FF 00 0F
13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00
E3 12 52 FE 93 0E 00 0F 93 01 80 00 63 16 D3 0F
13 02 00 00 B7 F0 0F F0 93 80 F0 00 13 FF F0 F0
13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00
93 02 20 00 E3 10 52 FE B7 FE 0F F0 93 8E FE 00
93 01 90 00 63 1A D3 0B 13 02 00 00 B7 10 F0 0F
93 80 00 FF 13 FF F0 70 13 02 12 00 93 02 20 00
E3 16 52 FE 93 0E 00 70 93 01 A0 00 63 16 DF 09
13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 00 00 00
13 FF 00 0F 13 02 12 00 93 02 20 00 E3 14 52 FE
93 0E 00 0F 93 01 B0 00 63 10 DF 07 13 02 00 00
B7 F0 0F F0 93 80 F0 00 13 00 00 00 13 00 00 00
13 FF F0 70 13 02 12 00 93 02 20 00 E3 12 52 FE
93 0E F0 00 93 01 C0 00 63 18 DF 03 93 70 00 0F
93 0E 00 00 93 01 D0 00 63 90 D0 03 B7 00 FF 00
93 80 F0 0F 13 F0 F0 70 93 0E 00 00 93 01 E0 00
63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00
6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00
@00000240
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00