2019-12-04 00:47:19 +00:00
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/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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2020-04-18 12:14:37 +00:00
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// 执行模块
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// 纯组合逻辑电路
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2020-03-29 15:19:14 +00:00
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module ex(
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2019-12-04 00:47:19 +00:00
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input wire rst,
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// from id
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2020-04-18 12:14:37 +00:00
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input wire[`InstBus] inst_i, // 指令内容
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input wire[`InstAddrBus] inst_addr_i, // 指令地址
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input wire reg_we_i, // 是否写通用寄存器
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input wire[`RegAddrBus] reg_waddr_i, // 写通用寄存器地址
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input wire[`RegBus] reg1_rdata_i, // 通用寄存器1输入数据
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input wire[`RegBus] reg2_rdata_i, // 通用寄存器2输入数据
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input wire csr_we_i, // 是否写CSR寄存器
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input wire[`MemAddrBus] csr_waddr_i, // 写CSR寄存器地址
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input wire[`RegBus] csr_rdata_i, // CSR寄存器输入数据
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input wire int_assert_i, // 中断发生标志
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input wire[`InstAddrBus] int_addr_i, // 中断跳转地址
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2020-08-13 01:01:27 +00:00
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input wire[`MemAddrBus] op1_i,
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input wire[`MemAddrBus] op2_i,
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input wire[`MemAddrBus] op1_jump_i,
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input wire[`MemAddrBus] op2_jump_i,
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2019-12-04 00:47:19 +00:00
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2020-03-29 15:19:14 +00:00
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// from mem
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2020-04-18 12:14:37 +00:00
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input wire[`MemBus] mem_rdata_i, // 内存输入数据
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2019-12-04 00:47:19 +00:00
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2020-01-13 00:26:41 +00:00
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// from div
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2020-04-18 12:14:37 +00:00
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input wire div_ready_i, // 除法运算完成标志
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input wire[`DoubleRegBus] div_result_i, // 除法运算结果
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input wire div_busy_i, // 除法运算忙标志
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input wire[2:0] div_op_i, // 具体是哪一条除法指令
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input wire[`RegAddrBus] div_reg_waddr_i,// 除法运算结束后要写的寄存器地址
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2020-03-29 15:19:14 +00:00
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// to mem
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2020-04-18 12:14:37 +00:00
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output reg[`MemBus] mem_wdata_o, // 写内存数据
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output reg[`MemAddrBus] mem_raddr_o, // 读内存地址
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output reg[`MemAddrBus] mem_waddr_o, // 写内存地址
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output wire mem_we_o, // 是否要写内存
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output wire mem_req_o, // 请求访问内存标志
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2019-12-04 00:47:19 +00:00
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// to regs
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2020-04-18 12:14:37 +00:00
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output wire[`RegBus] reg_wdata_o, // 写寄存器数据
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output wire reg_we_o, // 是否要写通用寄存器
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output wire[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
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2020-01-13 00:26:41 +00:00
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2020-04-05 14:22:34 +00:00
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// to csr reg
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2020-04-18 12:14:37 +00:00
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output reg[`RegBus] csr_wdata_o, // 写CSR寄存器数据
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output wire csr_we_o, // 是否要写CSR寄存器
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output wire[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址
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2020-04-05 14:22:34 +00:00
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2020-01-13 00:26:41 +00:00
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// to div
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2020-04-25 09:04:44 +00:00
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output wire div_start_o, // 开始除法运算标志
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2020-04-18 12:14:37 +00:00
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output reg[`RegBus] div_dividend_o, // 被除数
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output reg[`RegBus] div_divisor_o, // 除数
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output reg[2:0] div_op_o, // 具体是哪一条除法指令
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output reg[`RegAddrBus] div_reg_waddr_o,// 除法运算结束后要写的寄存器地址
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2020-01-13 00:26:41 +00:00
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2020-03-29 15:19:14 +00:00
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// to ctrl
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2020-04-18 12:14:37 +00:00
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output wire hold_flag_o, // 是否暂停标志
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output wire jump_flag_o, // 是否跳转标志
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output wire[`InstAddrBus] jump_addr_o // 跳转目的地址
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2019-12-04 00:47:19 +00:00
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2020-02-23 09:01:45 +00:00
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);
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2019-12-04 00:47:19 +00:00
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2020-03-29 15:19:14 +00:00
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wire[1:0] mem_raddr_index;
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wire[1:0] mem_waddr_index;
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2020-01-02 08:12:13 +00:00
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wire[`DoubleRegBus] mul_temp;
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2020-03-29 15:19:14 +00:00
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wire[`DoubleRegBus] mul_temp_invert;
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2020-08-13 01:01:27 +00:00
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wire[31:0] sr_shift;
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wire[31:0] sri_shift;
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wire[31:0] sr_shift_mask;
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wire[31:0] sri_shift_mask;
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wire[31:0] op1_add_op2_res;
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wire[31:0] op1_jump_add_op2_jump_res;
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wire[31:0] reg1_data_invert;
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wire[31:0] reg2_data_invert;
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wire op1_ge_op2_signed;
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wire op1_ge_op2_unsigned;
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wire op1_eq_op2;
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2020-03-29 15:19:14 +00:00
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reg[`RegBus] mul_op1;
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reg[`RegBus] mul_op2;
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2020-02-22 07:24:10 +00:00
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wire[6:0] opcode;
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wire[2:0] funct3;
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wire[6:0] funct7;
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wire[4:0] rd;
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2020-04-05 14:22:34 +00:00
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wire[4:0] uimm;
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2020-03-29 15:19:14 +00:00
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reg[`RegBus] reg_wdata;
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reg reg_we;
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reg[`RegAddrBus] reg_waddr;
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reg[`RegBus] div_wdata;
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reg div_we;
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reg[`RegAddrBus] div_waddr;
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reg div_hold_flag;
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reg div_jump_flag;
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reg[`InstAddrBus] div_jump_addr;
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reg hold_flag;
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reg jump_flag;
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reg[`InstAddrBus] jump_addr;
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2020-04-11 11:03:49 +00:00
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reg mem_we;
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reg mem_req;
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2020-04-25 09:04:44 +00:00
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reg div_start;
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2019-12-04 00:47:19 +00:00
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2020-02-22 07:24:10 +00:00
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assign opcode = inst_i[6:0];
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assign funct3 = inst_i[14:12];
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assign funct7 = inst_i[31:25];
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assign rd = inst_i[11:7];
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2020-04-05 14:22:34 +00:00
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assign uimm = inst_i[19:15];
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2019-12-04 00:47:19 +00:00
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2020-08-13 01:01:27 +00:00
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assign sr_shift = reg1_rdata_i >> reg2_rdata_i[4:0];
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assign sri_shift = reg1_rdata_i >> inst_i[24:20];
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assign sr_shift_mask = 32'hffffffff >> reg2_rdata_i[4:0];
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assign sri_shift_mask = 32'hffffffff >> inst_i[24:20];
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assign op1_add_op2_res = op1_i + op2_i;
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assign op1_jump_add_op2_jump_res = op1_jump_i + op2_jump_i;
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assign reg1_data_invert = ~reg1_rdata_i + 1;
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assign reg2_data_invert = ~reg2_rdata_i + 1;
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// 有符号数比较
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assign op1_ge_op2_signed = $signed(op1_i) >= $signed(op2_i);
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// 无符号数比较
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assign op1_ge_op2_unsigned = op1_i >= op2_i;
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assign op1_eq_op2 = (op1_i == op2_i);
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2020-01-02 08:12:13 +00:00
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2020-03-29 15:19:14 +00:00
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assign mul_temp = mul_op1 * mul_op2;
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assign mul_temp_invert = ~mul_temp + 1;
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2020-08-13 01:01:27 +00:00
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assign mem_raddr_index = (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 2'b11;
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assign mem_waddr_index = (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) & 2'b11;
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2020-02-16 13:27:11 +00:00
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2020-04-25 09:04:44 +00:00
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assign div_start_o = (int_assert_i == `INT_ASSERT)? `DivStop: div_start;
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2020-03-29 15:19:14 +00:00
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assign reg_wdata_o = reg_wdata | div_wdata;
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2020-04-18 12:14:37 +00:00
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// 响应中断时不写通用寄存器
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2020-04-11 11:03:49 +00:00
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assign reg_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: (reg_we || div_we);
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2020-03-29 15:19:14 +00:00
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assign reg_waddr_o = reg_waddr | div_waddr;
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2019-12-04 00:47:19 +00:00
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2020-04-18 12:14:37 +00:00
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// 响应中断时不写内存
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2020-04-11 11:03:49 +00:00
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assign mem_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: mem_we;
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2020-04-18 12:14:37 +00:00
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// 响应中断时不向总线请求访问内存
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2020-04-11 11:03:49 +00:00
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assign mem_req_o = (int_assert_i == `INT_ASSERT)? `RIB_NREQ: mem_req;
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2020-03-29 15:19:14 +00:00
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assign hold_flag_o = hold_flag || div_hold_flag;
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2020-04-11 11:03:49 +00:00
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assign jump_flag_o = jump_flag || div_jump_flag || ((int_assert_i == `INT_ASSERT)? `JumpEnable: `JumpDisable);
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assign jump_addr_o = (int_assert_i == `INT_ASSERT)? int_addr_i: (jump_addr | div_jump_addr);
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2020-01-13 00:26:41 +00:00
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2020-04-18 12:14:37 +00:00
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// 响应中断时不写CSR寄存器
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2020-04-11 11:03:49 +00:00
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assign csr_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: csr_we_i;
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2020-04-05 14:22:34 +00:00
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assign csr_waddr_o = csr_waddr_i;
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2020-03-29 15:19:14 +00:00
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2020-04-25 09:04:44 +00:00
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// 处理乘法指令
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2020-03-29 15:19:14 +00:00
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always @ (*) begin
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if (rst == `RstEnable) begin
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2020-05-02 03:58:44 +00:00
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mul_op1 = `ZeroWord;
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mul_op2 = `ZeroWord;
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2020-03-29 15:19:14 +00:00
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end else begin
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if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin
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2020-04-18 03:23:46 +00:00
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case (funct3)
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2020-05-02 03:58:44 +00:00
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`INST_MUL, `INST_MULHU: begin
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mul_op1 = reg1_rdata_i;
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mul_op2 = reg2_rdata_i;
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2020-04-18 03:23:46 +00:00
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end
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`INST_MULHSU: begin
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2020-08-13 01:01:27 +00:00
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mul_op1 = (reg1_rdata_i[31] == 1'b1)? (reg1_data_invert): reg1_rdata_i;
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2020-05-02 03:58:44 +00:00
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mul_op2 = reg2_rdata_i;
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2020-04-18 03:23:46 +00:00
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end
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`INST_MULH: begin
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2020-08-13 01:01:27 +00:00
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mul_op1 = (reg1_rdata_i[31] == 1'b1)? (reg1_data_invert): reg1_rdata_i;
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mul_op2 = (reg2_rdata_i[31] == 1'b1)? (reg2_data_invert): reg2_rdata_i;
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2020-04-18 03:23:46 +00:00
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end
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default: begin
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2020-05-02 03:58:44 +00:00
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mul_op1 = reg1_rdata_i;
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mul_op2 = reg2_rdata_i;
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2020-04-18 03:23:46 +00:00
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end
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endcase
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2020-03-29 15:19:14 +00:00
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end else begin
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2020-05-02 03:58:44 +00:00
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mul_op1 = reg1_rdata_i;
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mul_op2 = reg2_rdata_i;
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2020-03-08 07:09:30 +00:00
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end
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end
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end
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2020-04-25 09:04:44 +00:00
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// 处理除法指令
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2020-01-13 00:26:41 +00:00
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always @ (*) begin
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2020-02-22 07:24:10 +00:00
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if (rst == `RstEnable) begin
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2020-05-02 03:58:44 +00:00
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div_dividend_o = `ZeroWord;
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div_divisor_o = `ZeroWord;
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div_op_o = 3'b0;
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div_reg_waddr_o = `ZeroWord;
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div_waddr = `ZeroWord;
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div_hold_flag = `HoldDisable;
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div_we = `WriteDisable;
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div_wdata = `ZeroWord;
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div_start = `DivStop;
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div_jump_flag = `JumpDisable;
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div_jump_addr = `ZeroWord;
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2020-03-29 15:19:14 +00:00
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end else begin
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2020-05-02 03:58:44 +00:00
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div_dividend_o = reg1_rdata_i;
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div_divisor_o = reg2_rdata_i;
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div_op_o = funct3;
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div_reg_waddr_o = reg_waddr_i;
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2020-03-29 15:19:14 +00:00
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if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin
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2020-05-02 03:58:44 +00:00
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div_we = `WriteDisable;
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div_wdata = `ZeroWord;
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div_waddr = `ZeroWord;
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2020-03-29 15:19:14 +00:00
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case (funct3)
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2020-05-02 03:58:44 +00:00
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`INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin
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div_start = `DivStart;
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div_jump_flag = `JumpEnable;
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div_hold_flag = `HoldEnable;
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2020-08-13 01:01:27 +00:00
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div_jump_addr = op1_jump_add_op2_jump_res;
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2020-03-29 15:19:14 +00:00
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end
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default: begin
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2020-05-02 03:58:44 +00:00
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div_start = `DivStop;
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div_jump_flag = `JumpDisable;
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|
div_hold_flag = `HoldDisable;
|
|
|
|
|
div_jump_addr = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
div_jump_flag = `JumpDisable;
|
|
|
|
|
div_jump_addr = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (div_busy_i == `True) begin
|
2020-05-02 03:58:44 +00:00
|
|
|
div_start = `DivStart;
|
|
|
|
|
div_we = `WriteDisable;
|
|
|
|
|
div_wdata = `ZeroWord;
|
|
|
|
|
div_waddr = `ZeroWord;
|
|
|
|
|
div_hold_flag = `HoldEnable;
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
div_start = `DivStop;
|
|
|
|
|
div_hold_flag = `HoldDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (div_ready_i == `DivResultReady) begin
|
|
|
|
|
case (div_op_i)
|
2020-05-02 03:58:44 +00:00
|
|
|
`INST_DIV, `INST_DIVU: begin
|
|
|
|
|
div_wdata = div_result_i[31:0];
|
|
|
|
|
div_waddr = div_reg_waddr_i;
|
|
|
|
|
div_we = `WriteEnable;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
2020-05-02 03:58:44 +00:00
|
|
|
`INST_REM, `INST_REMU: begin
|
|
|
|
|
div_wdata = div_result_i[63:32];
|
|
|
|
|
div_waddr = div_reg_waddr_i;
|
|
|
|
|
div_we = `WriteEnable;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
div_wdata = `ZeroWord;
|
|
|
|
|
div_waddr = `ZeroWord;
|
|
|
|
|
div_we = `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
div_we = `WriteDisable;
|
|
|
|
|
div_wdata = `ZeroWord;
|
|
|
|
|
div_waddr = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
2020-05-02 03:58:44 +00:00
|
|
|
// 执行
|
2020-03-29 15:19:14 +00:00
|
|
|
always @ (*) begin
|
|
|
|
|
if (rst == `RstEnable) begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
mem_req = `RIB_NREQ;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
|
|
|
|
reg_we = `WriteDisable;
|
|
|
|
|
reg_waddr = `ZeroReg;
|
|
|
|
|
csr_wdata_o = `ZeroWord;
|
2020-02-22 07:24:10 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_we = reg_we_i;
|
|
|
|
|
reg_waddr = reg_waddr_i;
|
|
|
|
|
mem_req = `RIB_NREQ;
|
|
|
|
|
csr_wdata_o = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
|
|
|
|
|
case (opcode)
|
|
|
|
|
`INST_TYPE_I: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_ADDI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_add_op2_res;
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SLTI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = {32{(~op1_ge_op2_signed)}} & 32'h1;
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SLTIU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = {32{(~op1_ge_op2_unsigned)}} & 32'h1;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_XORI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i ^ op2_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_ORI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i | op2_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_ANDI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i & op2_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_SLLI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = reg1_rdata_i << inst_i[24:20];
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_SRI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (inst_i[30] == 1'b1) begin
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = (sri_shift & sri_shift_mask) | ({32{reg1_rdata_i[31]}} & (~sri_shift_mask));
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = reg1_rdata_i >> inst_i[24:20];
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_TYPE_R_M: begin
|
|
|
|
|
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
|
2020-01-02 08:12:13 +00:00
|
|
|
case (funct3)
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_ADD_SUB: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (inst_i[30] == 1'b0) begin
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i - op2_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_SLL: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i << op2_i[4:0];
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_SLT: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = {32{(~op1_ge_op2_signed)}} & 32'h1;
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SLTU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = {32{(~op1_ge_op2_unsigned)}} & 32'h1;
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_XOR: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i ^ op2_i;
|
2020-01-02 08:12:13 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_SR: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-02-22 07:24:10 +00:00
|
|
|
if (inst_i[30] == 1'b1) begin
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = (sr_shift & sr_shift_mask) | ({32{reg1_rdata_i[31]}} & (~sr_shift_mask));
|
2019-12-04 00:47:19 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = reg1_rdata_i >> reg2_rdata_i[4:0];
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
|
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
`INST_OR: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i | op2_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_AND: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_i & op2_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
2020-02-22 07:24:10 +00:00
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end else if (funct7 == 7'b0000001) begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_MUL: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = mul_temp[31:0];
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_MULHU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = mul_temp[63:32];
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_MULH: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
case ({reg1_rdata_i[31], reg2_rdata_i[31]})
|
|
|
|
|
2'b00: begin
|
|
|
|
|
reg_wdata = mul_temp[63:32];
|
|
|
|
|
end
|
|
|
|
|
2'b11: begin
|
|
|
|
|
reg_wdata = mul_temp[63:32];
|
|
|
|
|
end
|
|
|
|
|
2'b10: begin
|
|
|
|
|
reg_wdata = mul_temp_invert[63:32];
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
reg_wdata = mul_temp_invert[63:32];
|
|
|
|
|
end
|
|
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_MULHSU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (reg1_rdata_i[31] == 1'b1) begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = mul_temp_invert[63:32];
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = mul_temp[63:32];
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-02-22 07:24:10 +00:00
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_TYPE_L: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_LB: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_req = `RIB_REQ;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-05-02 03:58:44 +00:00
|
|
|
case (mem_raddr_index)
|
|
|
|
|
2'b00: begin
|
|
|
|
|
reg_wdata = {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]};
|
|
|
|
|
end
|
|
|
|
|
2'b01: begin
|
|
|
|
|
reg_wdata = {{24{mem_rdata_i[15]}}, mem_rdata_i[15:8]};
|
|
|
|
|
end
|
|
|
|
|
2'b10: begin
|
|
|
|
|
reg_wdata = {{24{mem_rdata_i[23]}}, mem_rdata_i[23:16]};
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
reg_wdata = {{24{mem_rdata_i[31]}}, mem_rdata_i[31:24]};
|
|
|
|
|
end
|
|
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_LH: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_req = `RIB_REQ;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (mem_raddr_index == 2'b0) begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]};
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = {{16{mem_rdata_i[31]}}, mem_rdata_i[31:16]};
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_LW: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_req = `RIB_REQ;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = mem_rdata_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_LBU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_req = `RIB_REQ;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-05-02 03:58:44 +00:00
|
|
|
case (mem_raddr_index)
|
|
|
|
|
2'b00: begin
|
|
|
|
|
reg_wdata = {24'h0, mem_rdata_i[7:0]};
|
|
|
|
|
end
|
|
|
|
|
2'b01: begin
|
|
|
|
|
reg_wdata = {24'h0, mem_rdata_i[15:8]};
|
|
|
|
|
end
|
|
|
|
|
2'b10: begin
|
|
|
|
|
reg_wdata = {24'h0, mem_rdata_i[23:16]};
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
reg_wdata = {24'h0, mem_rdata_i[31:24]};
|
|
|
|
|
end
|
|
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_LHU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_req = `RIB_REQ;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (mem_raddr_index == 2'b0) begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = {16'h0, mem_rdata_i[15:0]};
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
reg_wdata = {16'h0, mem_rdata_i[31:16]};
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_TYPE_S: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_SB: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
|
|
|
|
mem_we = `WriteEnable;
|
|
|
|
|
mem_req = `RIB_REQ;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_waddr_o = op1_add_op2_res;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-05-02 03:58:44 +00:00
|
|
|
case (mem_waddr_index)
|
|
|
|
|
2'b00: begin
|
|
|
|
|
mem_wdata_o = {mem_rdata_i[31:8], reg2_rdata_i[7:0]};
|
|
|
|
|
end
|
|
|
|
|
2'b01: begin
|
|
|
|
|
mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[7:0], mem_rdata_i[7:0]};
|
|
|
|
|
end
|
|
|
|
|
2'b10: begin
|
|
|
|
|
mem_wdata_o = {mem_rdata_i[31:24], reg2_rdata_i[7:0], mem_rdata_i[15:0]};
|
|
|
|
|
end
|
|
|
|
|
default: begin
|
|
|
|
|
mem_wdata_o = {reg2_rdata_i[7:0], mem_rdata_i[23:0]};
|
|
|
|
|
end
|
|
|
|
|
endcase
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_SH: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
|
|
|
|
mem_we = `WriteEnable;
|
|
|
|
|
mem_req = `RIB_REQ;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_waddr_o = op1_add_op2_res;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
if (mem_waddr_index == 2'b00) begin
|
2020-05-02 03:58:44 +00:00
|
|
|
mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[15:0]};
|
2020-03-29 15:19:14 +00:00
|
|
|
end else begin
|
2020-05-02 03:58:44 +00:00
|
|
|
mem_wdata_o = {reg2_rdata_i[15:0], mem_rdata_i[15:0]};
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
`INST_SW: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
|
|
|
|
mem_we = `WriteEnable;
|
|
|
|
|
mem_req = `RIB_REQ;
|
2020-08-13 01:01:27 +00:00
|
|
|
mem_waddr_o = op1_add_op2_res;
|
|
|
|
|
mem_raddr_o = op1_add_op2_res;
|
2020-05-02 03:58:44 +00:00
|
|
|
mem_wdata_o = reg2_rdata_i;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_TYPE_B: begin
|
|
|
|
|
case (funct3)
|
|
|
|
|
`INST_BEQ: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_flag = op1_eq_op2 & `JumpEnable;
|
|
|
|
|
jump_addr = {32{op1_eq_op2}} & op1_jump_add_op2_jump_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BNE: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_flag = (~op1_eq_op2) & `JumpEnable;
|
|
|
|
|
jump_addr = {32{(~op1_eq_op2)}} & op1_jump_add_op2_jump_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BLT: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_flag = (~op1_ge_op2_signed) & `JumpEnable;
|
|
|
|
|
jump_addr = {32{(~op1_ge_op2_signed)}} & op1_jump_add_op2_jump_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BGE: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_flag = (op1_ge_op2_signed) & `JumpEnable;
|
|
|
|
|
jump_addr = {32{(op1_ge_op2_signed)}} & op1_jump_add_op2_jump_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BLTU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_flag = (~op1_ge_op2_unsigned) & `JumpEnable;
|
|
|
|
|
jump_addr = {32{(~op1_ge_op2_unsigned)}} & op1_jump_add_op2_jump_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_BGEU: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_flag = (op1_ge_op2_unsigned) & `JumpEnable;
|
|
|
|
|
jump_addr = {32{(op1_ge_op2_unsigned)}} & op1_jump_add_op2_jump_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
`INST_JAL: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
jump_flag = `JumpEnable;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_addr = op1_jump_add_op2_jump_res;
|
|
|
|
|
reg_wdata = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_JALR: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
jump_flag = `JumpEnable;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_addr = op1_jump_add_op2_jump_res;
|
|
|
|
|
reg_wdata = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_LUI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
jump_flag = `JumpDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_AUIPC: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
jump_flag = `JumpDisable;
|
2020-08-13 01:01:27 +00:00
|
|
|
reg_wdata = op1_add_op2_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
2020-05-07 14:40:31 +00:00
|
|
|
`INST_NOP_OP: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
`INST_FENCE: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
|
|
|
|
jump_flag = `JumpEnable;
|
2020-08-13 01:01:27 +00:00
|
|
|
jump_addr = op1_jump_add_op2_jump_res;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
2020-04-05 14:22:34 +00:00
|
|
|
`INST_CSR: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
2020-04-05 14:22:34 +00:00
|
|
|
case (funct3)
|
|
|
|
|
`INST_CSRRW: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
csr_wdata_o = reg1_rdata_i;
|
|
|
|
|
reg_wdata = csr_rdata_i;
|
2020-04-05 14:22:34 +00:00
|
|
|
end
|
|
|
|
|
`INST_CSRRS: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
csr_wdata_o = reg1_rdata_i | csr_rdata_i;
|
|
|
|
|
reg_wdata = csr_rdata_i;
|
2020-04-05 14:22:34 +00:00
|
|
|
end
|
|
|
|
|
`INST_CSRRC: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
csr_wdata_o = csr_rdata_i & (~reg1_rdata_i);
|
|
|
|
|
reg_wdata = csr_rdata_i;
|
2020-04-05 14:22:34 +00:00
|
|
|
end
|
|
|
|
|
`INST_CSRRWI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
csr_wdata_o = {27'h0, uimm};
|
|
|
|
|
reg_wdata = csr_rdata_i;
|
2020-04-05 14:22:34 +00:00
|
|
|
end
|
|
|
|
|
`INST_CSRRSI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
csr_wdata_o = {27'h0, uimm} | csr_rdata_i;
|
|
|
|
|
reg_wdata = csr_rdata_i;
|
2020-04-05 14:22:34 +00:00
|
|
|
end
|
|
|
|
|
`INST_CSRRCI: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
csr_wdata_o = (~{27'h0, uimm}) & csr_rdata_i;
|
|
|
|
|
reg_wdata = csr_rdata_i;
|
2020-04-05 14:22:34 +00:00
|
|
|
end
|
|
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-04-05 14:22:34 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
2020-03-29 15:19:14 +00:00
|
|
|
default: begin
|
2020-05-02 03:58:44 +00:00
|
|
|
jump_flag = `JumpDisable;
|
|
|
|
|
hold_flag = `HoldDisable;
|
|
|
|
|
jump_addr = `ZeroWord;
|
|
|
|
|
mem_wdata_o = `ZeroWord;
|
|
|
|
|
mem_raddr_o = `ZeroWord;
|
|
|
|
|
mem_waddr_o = `ZeroWord;
|
|
|
|
|
mem_we = `WriteDisable;
|
|
|
|
|
reg_wdata = `ZeroWord;
|
2020-03-29 15:19:14 +00:00
|
|
|
end
|
|
|
|
|
endcase
|
2019-12-04 00:47:19 +00:00
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
endmodule
|
