282 lines
12 KiB
Plaintext
282 lines
12 KiB
Plaintext
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2020-04-24 Allen Baum <allen.baum@esperantotech.com>
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* fixed the I-SB-01.S and I-SH-01.S tests and associated reference signatures to account
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of tests with negative offsets (which causes stores outside the signature area)
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2020-03-19 Neel Gala <neelgala@gmail.com>
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* restructuring the riscv-test-suite to indicate clearly what is deprecated, wip and usable
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tests.
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* based on the above fixed the directory structure for riscv-targets where-ever applicable. Only
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tested riscvOVPsim and spike.
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* fixed script bugs for spike as well
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* renamed rv32i/I-IO.S to rv32i/I-IO-01.S along with necessary changes to the reference files
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and Makefrag
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* renamed mbadaddr csr to mtval as raised in issue #31
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* C.SWSP-01.S test updated to fix issue #37
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2020-03-18 Neel Gala <neelgala@gmail.com>
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* fixed doc/README.adoc with correct version to pass the sanity-check in the doc/Makefile
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2020-02-07 Prashanth Mundkur <prashanth.mundkur@gmail.com>
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* Support F extension on RV32 sail-riscv-c.
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2019-12-01 Allen Baum <allen.baum@esperantotech.com>
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* modified macro names to conformn to riscof naming convention of model specific vs. pre-defined
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* add more complete list of macros, their uses, parameters, and whether they are required or optional
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* minor structural changes (moving sentences, renumbering) and typo fixes
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* clarified impact of debug macros
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* clarified how SIGUPD and BASEUPD must be used
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* remove section about test taxonomy, binary tests, emulated ops
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* clarify/fix boundary between test target and framework responsibilities
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(split test target into test target and test shell)
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* remove To Be discussed items that have been discussed
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* remove default case condition; if conditions are unchanged, part of same case
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* minor grammatical changes related to the above
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2019-10-16 Allen Baum <allen.baum@esperantotech.com>
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* spec/TestFormatSpec.adoc: changed the format of the signature to fixed physical address size, fixed 32b data size extracted from COMPLIANCE_DATA_BEGIN/END range.
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* more gramatical fixes, clarifications added
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* added To Be Discussed items regarding emulated instruction and binary tests
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2019-09-11 Allen Baum <allen.baum@esperantotech.com>
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* spec/TestFormatSpec.adoc: more grammar and typo corrections and changes
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clarified and added To Be Discussed issues
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2019-09-11 Allen Baum <allen.baum@esperantotech.com>
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* spec/TestFormatSpec.adoc: many grammar and typo corrections and changes
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removed many "to Be Discussed items and made them official
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Added wording to clarify spec intent (work in progress/goal rather than final)
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Added macros to ease test authoring: RVTEST_SIGBASE, RVTEST_SIGUPDATE, RVTEST_CASE
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Added detail on proposals for connection to framework (how framework selects tests).
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Expanded definition of signature format
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Changed the (proposed) directory structure and naming convention to eliminate ambiguities, add consistancy and slightly better match existing structure
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Added many "future work" items related to the above
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Added examples and comments to code examples to indicate how proposed macros would be used
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* .gitignore: added condition to ignore Mac file system artifacts
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2019-11-05 Lee Moore <moore@imperas.com>
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* Restructured RV32I to move Zicsr and Zifencei into their own suites
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2019-10-14 Lee Moore <moore@imperas.com>
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* Added Ability to run a single test by using the Make Variable RISCV_TEST
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for example, to only run the test I-ADD-01 from the rv32i suite
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make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01
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* Added Top Level Variable to Makefile RISCV_TARGET_FLAGS,
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in the case of the RISCV_TARGET this can be passed and appended to the invocation
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commandline configuration, for example to pass a command line flag to the RISCV_TARGET
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to perform tracing. The value of this flag will be target specific
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make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 RISCV_TARGET_FLAGS="--trace"
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This is has also been added to all other targets to allow target configuration from
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the commandline
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2019-10-07 Philipp Wagner <phw@lowrisc.org>
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* When executing the test suite, Ibex always writes an instruction
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log. Update the Makefile to write it to a test-specific location
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(next to all other log files).
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* On Ibex, provide an additional .objdump-noalias disassembly file
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with no aliases and numeric register names (instead of ABI names).
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This file matches the Ibex trace and can be used to debug the test
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runs.
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2019-08-29 Robert Balas <balasr@iis.ee.ethz.ch>
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* Added support for using RI5CY as a target.
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* Added subdirectory riscv-target/ri5cy
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2019-08-08 Lee Moore <moore@imperas.com>
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* Added support for lowRISC/ibex RTL as a target using Verilator.
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In conjunction with Philipp Wagner of lowRISC phw@lowrisc.org
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2019-07-18 Paul Donahue <pdonahue@ventanamicro.com>
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* Fix typos/grammar and use correct architectural terms.
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2019-06-21 Ben Selfridge <benselfridge@galois.com>
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* Added support for using the the GRIFT simulator as a target.
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* Added subdirectory riscv-target/grift
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* updated README.md and doc/README.adoc
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2019-05-23 Prashanth Mundkur <prashanth.mundkur@gmail.com>
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* Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
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* added subdirectories riscv-target/sail-riscv-c and riscv-target/sail-riscv-ocaml
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* updated README.md and doc/README.adoc
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2019-04-05 Allen Baum <allen.baum@esperantotech.com>
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* spec/TestFormatSpec.adoc: Adding details, minor corrections, ToBeDiscussed
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items and clarifications to the specification of the future compliance test
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suite. Also removing restrictions on having absolate addresses in signature
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2019-02-21 Lee Moore <moore@imperas.com>
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* Fixed bug in RVTEST_IO_ASSERT_GPR_EQ which was not preserving register t0
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* Corrected commit I-LUI-01.S, register target changed but missed assertion
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2019-02-21 Deborah Soung <debs@sifive.com>
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* added RiscvFormalSpec as a target with its own unique environment
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2019-02-15 Radek Hajek <radek.hajek@codasip.com>
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* updated rv32i tests to support all registers (x31) with assertions
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* updated spec/TestFormatSpec.adoc example ISA test with new assertions
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2019-02-05 Deborah Soung <debs@sifive.com>
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* [Issue #33] fixing rv32si/ma_fetch.S test
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* [Issue #32] fixing breakpoint test
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2019-02-01 Lee Moore <moore@imperas.com>
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* updated Infrastructure macros to support non-volatile registers
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* updated riscvOVPsim
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2019-01-29 Deborah Soung <debs@sifive.com>
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* Added Rocket Chip generated cores as a target
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* riscv-target/rocket/compliance_io.h created
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* riscv-target/rocket/compliance_test.h created
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* riscv-target/rocket/*/Makefile.include created for existing test suites
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* README.adoc updated with instructions for using Rocket cores as targets
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2019-01-22 Premysl Vaclavik <pvaclavik@codasip.com>
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* feature: initial version of Compliance Test Format Specification
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* This new document outlines how we should like the compliance
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system to work going forward. By contrast the doc/README.adoc file
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describes the current system as it is.
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* Approved at Compliance TG meeting of 9 Jan 2019.
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2019-01-02 Radek Hajek <radek.hajek@codasip.com>
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* unified macros in all compliance tests
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2018-12-20 Lee Moore <moore@imperas.com>
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* fixed riscvOVPsim
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2018-11-22 Simon Davidmann <simond@imperas.com>
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* added information on test suite status
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2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
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* Added support for using external target directories with $TARGETDIR
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2018-11-21 Neel Gala <neelgala@incoresemi.com>
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* riscv-test-suite/rv_/references/_.reference_output: changed signature
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format for all tests to include only 4-bytes per line starting with the
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most significant byte on the left.
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* riscv-target/spike/device/rv_/Makefile.include: Added a patch for
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spike-device Makefiles where the old-signature format is post-processed
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to generate a signature in the new format at the end of each test.
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* riscv-target/riscvOVPsim/device/rv_/Makefile.include: same patch as above.
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* Makefile: default target for Makefile is now to run all tests supported by
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the target mentioned defined by RISCV_TARGET variable.
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2018-10-11 Simon Davidmann <simond@imperas.com>
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* Ported github riscv/riscv-tests for RV32 processors to this compliance env
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* rv32ua rv32uc rv32ud rv32uf rv32ud rv32ui
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2018-09-10 Lee Moore <moore@imperas.com>
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* Added tests to RV32I to improve coverage, usage of Imperas Mutating Fault Simulator to
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identify untested usage cases
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* Macro renames to support GPR, (S)FPR, (D)FPR
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* Added test suite RV32IM to test 32 bit Multiply and Divide instructions
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* Added test suite RV32IMC to test 32 bit Compressed instructions
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* Added test suite RV64I to test 64 bit Integer instructions
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* Added test suite RV64IM to test 64 bit Multiply and Divide instructions
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2018-06-15 Radek Hajek <hajek@codasip.com>
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Modifications to support Codasip simulator.
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The simulator is renamed as Codasip-simulator (was
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Codasip-IA-simulator), compliance_test.h has been moved to target
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directories and a COMPILE_TARGET has been added to Makefile to
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allow use of LLVM.
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* Makefile: Include Codasip simulator target.
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* riscv-target/codasip-IA-simulator/compliance_io.h: Renamed as
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riscv-target/Codasip-simulator/compliance_io.h.
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* riscv-target/Codasip-simulator/compliance_io.h: Renamed from
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riscv-target/codasip-IA-simulator/compliance_io.
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* riscv-target/Codasip-simulator/compliance_test.h: Created.
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* riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include:
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Renamed as
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riscv-target/Codasip-simulator/device/rv32i/Makefile.include
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* riscv-target/Codasip-simulator/device/rv32i/Makefile.include:
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Renamed from
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riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include.
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* riscv-test-env/compliance_test.h: Renamed as
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riscv-target/riscvOVPsim/compliance_test.h.
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* riscv-target/riscvOVPsim/compliance_test.h: Renamed from
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riscv-test-env/compliance_test.h.
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* riscv-target/riscvOVPsim/device/rv32i/Makefile.include: Updated
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for new environment.
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* riscv-target/spike/compliance_test.h: Created.
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* riscv-target/spike/device/rv32i/Makefile.include: Updated for
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new environment.
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* riscv-test-suite/rv32i/Makefile: Likewise.
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2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
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Put placeholders in empty directories to make sure they show in
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the GitHub hierarchy.
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* riscv-test-suite/rv32i/.gitignore: Created.
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* riscv-test-suite/rv32m/.gitignore: Created.
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2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
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* README.md: Make references to files in the repo into links.
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2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
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* .gitignore: Ignore editor backup files.
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2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
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* README.md: Add better link to documentation README.md.
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2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
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* README.md: Move AsciiDoc details into new README.md in the doc
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directory.
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2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
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* README.md: Fix typo in link to AsciiDoc cheat sheet
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2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
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* COPYING.BSD: Created.
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* COPYING.CC: Created.
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* README.md: Add git process, licensing and engineering process.
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2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
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* README.md: Correct details for running the compliance tests and
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directory for OVPsim.
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2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
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Clean restructuring to just the work of interest.
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* thought-experiments: Directory removed.
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* .gitignore: Merged with TestStructure/.gitignore
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* Makefile: Renamed from TestStructure/Makefile.
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* TestStructure/Makefile: Renamed as Makefile.
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* README.md: Merged with TestStructure/README.md.
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* TestStructure/.gitignore: Deleted and contents moved into
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.gitignore.
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* TestStructure/README.md: Deleted and contents moved into
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README.md.
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* TestStructure/doc: Directory deleted.
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* TestStructure/riscv-target: Directory moved to riscv-target.
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* riscv-target: Directory moved from TestStructure/riscv-target
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* TestStructure/riscv-test-env: Directory moved to riscv-test-env.
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* riscv-test-env: Directory moved from
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TestStructure/riscv-test-env.
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* TestStructure/riscv-test-suite: Directory moved to
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riscv-test-suite.
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* riscv-test-suite: Directory moved from
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TestStructure/riscv-test-suite.
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* thought-experiments: Directory deleted.
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2018-05-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
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Initial commit to populate the repository.
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* ChangeLog: Created.
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* README.md: Created.
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