fccc55225a
This adds example config and flash driver for russian Cortex-M3 microcontroller model. Run-time tested on MDR32F9Q2I evaluation board; the flash driver should be compatible with MDR32F2x (Cortex-M0) too but I lack hardware to test. There're no status bits at all, the datasheets specifies some delays for flash operations instead. All being in <100us range, they're hard to violate with JTAG, I hope. There're also no flash identification registers so the flash size and type has to be hardcoded into the config. The flashing is considerably complicated because the flash is split into pages, and each page consists of 4 interleaved non-consecutive "sectors" (on MDR32F9 only, MDR32F2 is single-sectored), so the fastest way is to latch the page and sector address and then write only the part that should go into the current page and current sector. Performance testing results with adapter_khz 1000 and the chip running on its default HSI 8MHz oscillator: When working area is specified, a target helper algorithm is used: wrote 131072 bytes from file testfile.bin in 3.698427s (34.609 KiB/s) This can theoretically be sped up by ~1.4 times if the helper algorithm is fed some kind of "loader instructions stream" to allow sector-by-sector writing. Pure JTAG implementation (when target memory area is not available) flashes all the 128k memory in 49.5s. Flashing "info" memory region is also implemented, but due to the overlapping memory addresses (resulting in incorrect memory map calculations for GDB) it can't be used at the same time, so OpenOCD needs to be started this way: -c "set IMEMORY true" -f target/mdr32f9q2i.cfg It also can't be read/verified because it's not memory-mapped anywhere ever, and OpenOCD NOR framework doesn't really allow to provide a custom handler that would be used when verifying. Change-Id: I80c0632da686d49856fdbf9e05d908846dd44316 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1532 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> |
||
|---|---|---|
| .. | ||
| checksum | ||
| erase_check | ||
| flash | ||
| README | ||
README
Included in these directories are the src to the various ram loaders used within openocd. ** target checksum loaders ** checksum/armv4_5_crc.s : - ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code checksum/armv7m_crc.s : - ARMv7m checksum loader : see target/armv7m.c:cortex_m3_crc_code checksum/mips32.s : - MIPS32 checksum loader : see target/mips32.c:mips_crc_code ** target flash loaders ** flash/pic32mx.s : - Microchip PIC32 flash loader : see flash/nor/pic32mx.c:pic32mx_flash_write_code flash/stellaris.s : - TI Stellaris flash loader : see flash/nor/stellaris.c:stellaris_write_code flash/stm32x.s : - ST STM32 flash loader : see flash/nor/stm32x.c:stm32x_flash_write_code flash/str7x.s : - ST STR7 flash loader : see flash/nor/str7x.c:str7x_flash_write_code flash/str9x.s : - ST STR9 flash loader : see flash/nor/str9x.c:str9x_flash_write_code Spencer Oliver spen@spen-soft.co.uk