223 lines
7.5 KiB
ArmAsm
223 lines
7.5 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2012 by George Harris *
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* george@luminairecoffee.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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/*
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* Params :
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* r0 = workarea start, status (out)
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* r1 = workarea end
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* r2 = target address (offset from flash base)
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* r3 = count (bytes)
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* r4 = page size
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* Clobbered:
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* r7 - rp
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* r8 - wp, tmp
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* r9 - send/receive data
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* r10 - temp
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* r11 - current page end address
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*/
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/*
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* This code is embedded within: src/flash/nor/lpcspifi.c as a "C" array.
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*
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* To rebuild:
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* arm-none-eabi-gcc -c lpcspifi_write.S
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* arm-none-eabi-objcopy -O binary lpcspifi_write.o lpcspifi_write.bin
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* xxd -c 8 -i lpcspifi_write.bin > lpcspifi_write.txt
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*
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* Then read and edit this result into the "C" source.
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*/
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#define SSP_BASE_HIGH 0x4008
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#define SSP_BASE_LOW 0x3000
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#define SSP_CR0_OFFSET 0x00
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#define SSP_CR1_OFFSET 0x04
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#define SSP_DATA_OFFSET 0x08
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#define SSP_CPSR_OFFSET 0x10
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#define SSP_SR_OFFSET 0x0c
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#define SSP_CLOCK_BASE_HIGH 0x4005
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#define SSP_CLOCK_BASE_LOW 0x0000
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#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
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#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
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#define SSP_BASE_CLOCK_OFFSET 0x94
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#define SSP_BRANCH_CLOCK_OFFSET 0x700
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#define IOCONFIG_BASE_HIGH 0x4008
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#define IOCONFIG_BASE_LOW 0x6000
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#define IOCONFIG_SCK_OFFSET 0x18c
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#define IOCONFIG_HOLD_OFFSET 0x190
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#define IOCONFIG_WP_OFFSET 0x194
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#define IOCONFIG_MISO_OFFSET 0x198
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#define IOCONFIG_MOSI_OFFSET 0x19c
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#define IOCONFIG_CS_OFFSET 0x1a0
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#define IO_BASE_HIGH 0x400f
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#define IO_BASE_LOW 0x4000
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#define IO_CS_OFFSET 0xab
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#define IODIR_BASE_HIGH 0x400f
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#define IODIR_BASE_LOW 0x6000
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#define IO_CS_DIR_OFFSET 0x14
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setup: /* Initialize SSP pins and module */
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mov.w r10, #IOCONFIG_BASE_LOW
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movt r10, #IOCONFIG_BASE_HIGH
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mov.w r8, #0xea
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str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
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mov.w r8, #0x40
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str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
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mov.w r8, #0x40
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str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
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mov.w r8, #0xed
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str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
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mov.w r8, #0xed
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str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
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mov.w r8, #0x44
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str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
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mov.w r10, #IODIR_BASE_LOW
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movt r10, #IODIR_BASE_HIGH
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mov.w r8, #0x800
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str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
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mov.w r10, #IO_BASE_LOW
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movt r10, #IO_BASE_HIGH
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mov.w r8, #0xff
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str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
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mov.w r10, #SSP_CLOCK_BASE_LOW
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movt r10, #SSP_CLOCK_BASE_HIGH
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mov.w r8, #0x0000
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movt r8, #0x0100
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str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
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mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
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movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
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mov.w r8, #0x01
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str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
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mov.w r10, #SSP_BASE_LOW
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movt r10, #SSP_BASE_HIGH
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mov.w r8, #0x07
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str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
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mov.w r8, #0x02
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str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
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str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
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mov.w r11, #0x00
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find_next_page_boundary:
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add r11, r4 /* Increment to the next page */
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cmp r11, r2
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/* If we have not reached the next page boundary after the target address, keep going */
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bls find_next_page_boundary
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write_enable:
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bl cs_down
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mov.w r9, #0x06 /* Send the write enable command */
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bl write_data
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bl cs_up
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bl cs_down
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mov.w r9, #0x05 /* Get status register */
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bl write_data
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mov.w r9, #0x00 /* Dummy data to clock in status */
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bl write_data
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bl cs_up
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tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
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beq error
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page_program:
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bl cs_down
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mov.w r9, #0x02 /* Send the page program command */
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bl write_data
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write_address:
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lsr r9, r2, #16 /* Send the current 24-bit write address, MSB first */
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bl write_data
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lsr r9, r2, #8
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bl write_data
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mov.w r9, r2
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bl write_data
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wait_fifo:
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ldr r8, [r0] /* read the write pointer */
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cmp r8, #0 /* if it's zero, we're gonzo */
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beq exit
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ldr r7, [r0, #4] /* read the read pointer */
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cmp r7, r8 /* wait until they are not equal */
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beq wait_fifo
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write:
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ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
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bl write_data /* send the byte to the flash chip */
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cmp r7, r1 /* wrap the read pointer if it is at the end */
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it cs
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addcs r7, r0, #8 /* skip loader args */
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str r7, [r0, #4] /* store the new read pointer */
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subs r3, r3, #1 /* decrement count */
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cbz r3, exit /* Exit if we have written everything */
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add r2, #1 /* Increment flash address by 1 */
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cmp r11, r2 /* See if we have reached the end of a page */
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bne wait_fifo /* If not, keep writing bytes */
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bl cs_up /* Otherwise, end the command and keep going w/ the next page */
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add r11, r4 /* Move up the end-of-page address by the page size*/
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wait_flash_busy: /* Wait for the flash to finish the previous page write */
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bl cs_down
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mov.w r9, #0x05 /* Get status register */
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bl write_data
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mov.w r9, #0x00 /* Dummy data to clock in status */
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bl write_data
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bl cs_up
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tst r9, #0x01 /* If it isn't done, keep waiting */
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bne wait_flash_busy
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b write_enable /* If it is done, start a new page write */
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write_data: /* Send/receive 1 byte of data over SSP */
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mov.w r10, #SSP_BASE_LOW
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movt r10, #SSP_BASE_HIGH
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str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
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wait_transmit:
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ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
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tst r9, #0x0010 /* Check if BSY bit is set */
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bne wait_transmit /* If still transmitting, keep waiting */
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ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
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bx lr /* Exit subroutine */
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cs_up:
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mov.w r8, #0xff
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b cs_write
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cs_down:
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mov.w r8, #0x0000
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cs_write:
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mov.w r10, #IO_BASE_LOW
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movt r10, #IO_BASE_HIGH
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str.w r8, [r10, #IO_CS_OFFSET]
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bx lr
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error:
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movs r0, #0
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str r0, [r2, #4] /* set rp = 0 on error */
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exit:
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bl cs_up /* end the command before returning */
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mov r0, r6
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bkpt #0x00
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.end
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