103 lines
4.2 KiB
ArmAsm
103 lines
4.2 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2012 by George Harris *
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* george@luminairecoffee.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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/***************************************************************************
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* This is an algorithm for the LPC43xx family (and probably the LPC18xx *
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* family as well, though they have not been tested) that will initialize *
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* memory-mapped SPI flash accesses. Unfortunately NXP has published *
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* neither the ROM source code that performs this initialization nor the *
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* register descriptions necessary to do so, so this code is necessary to *
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* call into the ROM SPIFI API. *
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***************************************************************************/
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.text
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.syntax unified
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.arch armv7-m
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.thumb
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.thumb_func
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.align 2
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/*
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* Params :
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* r0 = spifi clock speed
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*/
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#define IOCONFIG_BASE_HIGH 0x4008
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#define IOCONFIG_BASE_LOW 0x6000
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#define IOCONFIG_SCK_OFFSET 0x18c
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#define IOCONFIG_HOLD_OFFSET 0x190
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#define IOCONFIG_WP_OFFSET 0x194
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#define IOCONFIG_MISO_OFFSET 0x198
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#define IOCONFIG_MOSI_OFFSET 0x19c
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#define IOCONFIG_CS_OFFSET 0x1a0
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#define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
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#define SPIFI_ROM_TABLE_BASE_LOW 0x0118
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code:
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mov.w r8, r0
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sub sp, #0x84
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add r7, sp, #0x0
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/* Initialize SPIFI pins */
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mov.w r3, #IOCONFIG_BASE_LOW
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movt r3, #IOCONFIG_BASE_HIGH
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mov.w r2, #0xf3
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str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
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mov.w r3, #IOCONFIG_BASE_LOW
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movt r3, #IOCONFIG_BASE_HIGH
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mov.w r2, #IOCONFIG_BASE_LOW
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movt r2, #IOCONFIG_BASE_HIGH
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mov.w r1, #IOCONFIG_BASE_LOW
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movt r1, #IOCONFIG_BASE_HIGH
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mov.w r0, #IOCONFIG_BASE_LOW
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movt r0, #IOCONFIG_BASE_HIGH
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mov.w r4, #0xd3
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str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
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mov r0, r4
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str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
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mov r1, r0
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str.w r1, [r2, #IOCONFIG_WP_OFFSET]
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str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
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mov.w r3, #IOCONFIG_BASE_LOW
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movt r3, #IOCONFIG_BASE_HIGH
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mov.w r2, #0x13
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str.w r2, [r3, #IOCONFIG_CS_OFFSET]
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/* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
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/* on initialization arguments. */
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movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
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movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
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ldr r3, [r3, #0x0]
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ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
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/* Set up function arguments */
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movw r0, #0x3b4
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movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
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mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
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mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
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mov.w r3, r8 /* SPIFI clock speed (12MHz) */
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blx r4 /* Call the init function */
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b done
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done:
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bkpt #0
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.end
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