tinyriscv-openocd/tcl/cpld
Robert Jordens 7944ebb694 xilinx-xcu: add Xilinx Ultrascale tap data
The Ultrascale series is a bit more complicated to handle since with the
stacked and interconnected dies the IR gets longer. This adds support
for all currently known chips from the Ultrascale family.

Change-Id: Ibac325dd6fadc76f73cc682b1c62c1a5f39f0786
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4188
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30 10:07:49 +01:00
..
altera-5m570z-cpld.cfg
altera-epm240.cfg
jtagspi.cfg jtagspi: new protocol that includes transfer length 2018-01-13 19:36:42 +00:00
lattice-lc4032ze.cfg
xilinx-xc6s.cfg
xilinx-xc7.cfg
xilinx-xcf-p.cfg
xilinx-xcf-s.cfg
xilinx-xcr3256.cfg
xilinx-xcu.cfg xilinx-xcu: add Xilinx Ultrascale tap data 2018-03-30 10:07:49 +01:00