d25355473d
Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> |
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| .. | ||
| libdcc | ||
| loaders | ||
| remote_bitbang | ||
| rpc_examples | ||
| rtos-helpers | ||
| xsvf_tools | ||
| 99-openocd.rules | ||
| coresight-trace.txt | ||
| cross-build.sh | ||
| gen-stellaris-part-header.pl | ||
| itmdump.c | ||