134 lines
3.5 KiB
Tcl
134 lines
3.5 KiB
Tcl
# MEMORY
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#
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# All Memory regions have two components.
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# (1) A count of regions, in the form N_NAME
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# (2) An array within info about each region.
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#
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# The ARRAY
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#
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# <NAME>( RegionNumber , ATTRIBUTE )
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#
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# Where <NAME> is one of:
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#
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# N_FLASH & FLASH (internal memory)
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# N_RAM & RAM (internal memory)
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# N_MMREGS & MMREGS (for memory mapped registers)
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# N_XMEM & XMEM (off chip memory, ie: flash on cs0, sdram on cs2)
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# or N_UNKNOWN & UNKNOWN for things that do not exist.
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#
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# We have 1 unknown region.
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set N_UNKNOWN 1
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# All MEMORY regions must have these attributes
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# CS - chip select (if internal, use -1)
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set UNKNOWN(0,CHIPSELECT) -1
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# BASE - base address in memory
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set UNKNOWN(0,BASE) 0
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# LEN - length in bytes
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set UNKNOWN(0,LEN) $CPU_MAX_ADDRESS
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# HUMAN - human name of the region
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set UNKNOWN(0,HUMAN) "unknown"
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# TYPE - one of:
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# flash, ram, mmr, unknown
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# For harvard arch:
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# iflash, dflash, iram, dram
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set UNKNOWN(0,TYPE) "unknown"
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# RWX - access ablity
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# unix style chmod bits
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# 0 - no access
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# 1 - execute
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# 2 - write
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# 4 - read
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# hence: 7 - readwrite execute
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set RWX_NO_ACCESS 0
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set RWX_X_ONLY $BIT0
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set RWX_W_ONLY $BIT1
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set RWX_R_ONLY $BIT2
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set RWX_RW [expr $RWX_R_ONLY + $RWX_W_ONLY]
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set RWX_R_X [expr $RWX_R_ONLY + $RWX_X_ONLY]
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set RWX_RWX [expr $RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY]
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set UNKNOWN(0,RWX) $RWX_NO_ACCESS
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# WIDTH - access width
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# 8,16,32 [0 means ANY]
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set ACCESS_WIDTH_NONE 0
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set ACCESS_WIDTH_8 $BIT0
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set ACCESS_WIDTH_16 $BIT1
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set ACCESS_WIDTH_32 $BIT2
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set ACCESS_WIDTH_ANY [expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32]
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set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
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proc iswithin { ADDRESS BASE LEN } {
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return [expr ((($ADDRESS - $BASE) > 0) && (($ADDRESS - $BASE + $LEN) > 0))]
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}
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proc address_info { ADDRESS } {
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foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
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if { info exists $WHERE } {
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set lmt [set N_[set WHERE]]
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for { set region 0 } { $region < $lmt } { incr region } {
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if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {
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return "$WHERE $region";
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}
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}
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}
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}
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# Return the 'unknown'
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return "UNKNOWN 0"
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}
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proc memread32 {ADDR} {
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set foo(0) 0
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if ![ catch { mem2array foo 32 $ADDR 1 } msg ] {
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return $foo(0)
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} else {
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error "memread32: $msg"
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}
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}
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proc memread16 {ADDR} {
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set foo(0) 0
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if ![ catch { mem2array foo 16 $ADDR 1 } msg ] {
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return $foo(0)
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} else {
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error "memread16: $msg"
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}
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}
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proc memread8 {ADDR} {
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set foo(0) 0
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if ![ catch { mem2array foo 8 $ADDR 1 } msg ] {
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return $foo(0)
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} else {
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error "memread8: $msg"
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}
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}
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proc memwrite32 {ADDR DATA} {
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set foo(0) $DATA
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if ![ catch { array2mem foo 32 $ADDR 1 } msg ] {
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return $foo(0)
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} else {
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error "memwrite32: $msg"
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}
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}
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proc memwrite16 {ADDR DATA} {
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set foo(0) $DATA
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if ![ catch { array2mem foo 16 $ADDR 1 } msg ] {
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return $foo(0)
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} else {
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error "memwrite16: $msg"
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}
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}
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proc memwrite8 {ADDR DATA} {
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set foo(0) $DATA
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if ![ catch { array2mem foo 8 $ADDR 1 } msg ] {
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return $foo(0)
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} else {
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error "memwrite8: $msg"
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}
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}
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