3ace333663
This config is only lightly tested, and doesn't work well yet; but it's a start. * Notably missing is PLL configuration, since each DaVinci does that just a bit differently; and thus DDR2 setup. * The SRST workaround needed for the goof in the CPLD's VHDL depends on at least the not-yet-merged patch letting ARM9 (and ARM7) chips perform resets that don't use SRST. So this isn't yet suitable for debugging U-Boot. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> |
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board | ||
chip | ||
cpld | ||
cpu/arm | ||
interface | ||
target | ||
test | ||
bitsbytes.tcl | ||
memory.tcl | ||
mmr_helpers.tcl | ||
readable.tcl |