tinyriscv-openocd/contrib/loaders/checksum
Tim Newsome bb03f79bde
Improve block read and checksum speed (#381)
* Cache program buffer writes.

Speeds up flash program by 3%, flash verify by 2%.

Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a

* Remove nop from batch reads.

program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287
KiB/s, verify @ 23.148 KiB/s originally).

Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935

* Use "algorithm" to compute CRC on RISC-V targets.

Use the C compiler to generate the algorithm code. It's better at
assembly than I am. We need separate RV32 and RV64 binaries to handle
shift instructions. I used the code from gdb (libiberty really) because
it returns the correct result. I'm not sure if the table is worth it
since we do have to save/download/restore more bytes now.

riscv_run_algorithm() now properly saves and reads back all registers
used for parameters. It also doesn't check final_pc if exit_point is 0.
Using gdb means I don't know the exact address where the code will end.

Small target.[ch] change to be able to run algorithms at 64-bit
addresses.

Flashing an arty board now:
```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s)
verified 2192012 bytes in 7.037476s (304.177 KiB/s)
9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k
```

Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190

* Clean up formatting.

Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 10:56:37 -07:00
..
Makefile Improve block read and checksum speed (#381) 2019-06-19 10:56:37 -07:00
armv4_5_crc.inc armv4_5: Integrate build of checksum code 2016-05-22 15:51:15 +01:00
armv4_5_crc.s update files to correct FSF address 2013-06-05 19:52:42 +00:00
armv7m_crc.inc armv7m: Integrate build of checksum code 2016-05-22 15:49:51 +01:00
armv7m_crc.s update files to correct FSF address 2013-06-05 19:52:42 +00:00
mips32.s update files to correct FSF address 2013-06-05 19:52:42 +00:00
riscv32_crc.inc Improve block read and checksum speed (#381) 2019-06-19 10:56:37 -07:00
riscv64_crc.inc Improve block read and checksum speed (#381) 2019-06-19 10:56:37 -07:00
riscv_crc.c Improve block read and checksum speed (#381) 2019-06-19 10:56:37 -07:00