124 lines
4.3 KiB
INI
124 lines
4.3 KiB
INI
# Marvell OpenRD
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source [find interface/openrd.cfg]
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source [find target/feroceon.cfg]
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$_TARGETNAME configure \
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-work-area-phys 0x10000000 \
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-work-area-size 65536 \
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-work-area-backup 0
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arm7_9 dcc_downloads enable
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# this assumes the hardware default peripherals location before u-Boot moves it
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set _FLASHNAME $_CHIPNAME.flash
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nand device $_FLASHNAME orion 0 0xd8000000
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proc openrd_init { } {
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# We need to assert DBGRQ while holding nSRST down.
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# However DBGACK will be set only when nSRST is released.
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# Furthermore, the JTAG interface doesn't respond at all when
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# the CPU is in the WFI (wait for interrupts) state, so it is
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# possible that initial tap examination failed. So let's
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# re-examine the target again here when nSRST is asserted which
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# should then succeed.
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jtag_reset 0 1
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feroceon.cpu arp_examine
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halt 0
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jtag_reset 0 0
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wait_halt
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arm mcr 15 0 0 1 0 0x00052078
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mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
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mww 0xD0001404 0x37543000 # Dunit Control Low Register
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mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
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mww 0xD000140C 0x00000A33 # DDR SDRAM Timing (High) Register
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mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
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mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
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mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
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mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
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mww 0xD0001420 0x00000004 # DDR SDRAM Extended Mode Register
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mww 0xD0001424 0x0000F17F # Dunit Control High Register
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mww 0xD0001428 0x00085520 # Dunit Control High Register
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mww 0xD000147c 0x00008552 # Dunit Control High Register
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mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
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mww 0xD0001508 0x10000000 # CS1n Base Register
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mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
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mww 0xD0001514 0x00000000 # CS2n Size Register
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mww 0xD000151C 0x00000000 # CS3n Size Register
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mww 0xD0001494 0x00120012 # DDR2 SDRAM ODT Control (Low) Register
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mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
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mww 0xD000149C 0x0000E40F # DDR2 Dunit ODT Control Register
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mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
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mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0020204 0x00000000 # "
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mww 0xD0010000 0x01111111 # MPP 0 to 7
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mww 0xD0010004 0x11113322 # MPP 8 to 15
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mww 0xD0010008 0x00001111 # MPP 16 to 23
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mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
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mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
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mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
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}
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proc openrd_reflash_uboot { } {
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# reflash the u-Boot binary and reboot into it
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openrd_init
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nand probe 0
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nand erase 0 0x0 0xa0000
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nand write 0 uboot.bin 0 oob_softecc_kw
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resume
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}
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proc openrd_load_uboot { } {
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# load u-Boot into RAM and execute it
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openrd_init
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load_image uboot.elf
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verify_image uboot.elf
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resume 0x00600000
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}
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