88 lines
2.1 KiB
INI
88 lines
2.1 KiB
INI
#
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# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
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#
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adapter_khz 500
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc4370
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}
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#
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# M4 JTAG mode TAP
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#
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if { [info exists M4_JTAG_TAPID] } {
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set _M4_JTAG_TAPID $M4_JTAG_TAPID
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} else {
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set _M4_JTAG_TAPID 0x4ba00477
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}
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#
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# M4 SWD mode TAP
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#
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if { [info exists M4_SWD_TAPID] } {
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set _M4_SWD_TAPID $M4_SWD_TAPID
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} else {
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set _M4_SWD_TAPID 0x2ba01477
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}
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source [find target/swj-dp.tcl]
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if { [using_jtag] } {
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set _M4_TAPID $_M4_JTAG_TAPID
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} else {
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set _M4_TAPID $_M4_SWD_TAPID
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}
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#
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# M0 TAP
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#
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if { [info exists M0_JTAG_TAPID] } {
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set _M0_JTAG_TAPID $M0_JTAG_TAPID
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} else {
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set _M0_JTAG_TAPID 0x0ba01477
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}
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swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M4_TAPID
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dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
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target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
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# LPC4370 has 96+32 KB contiguous SRAM
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x20000
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}
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$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
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-work-area-size $_WORKAREASIZE -work-area-backup 0
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if { [using_jtag] } {
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jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M0_JTAG_TAPID
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jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M0_JTAG_TAPID
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dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
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dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
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target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
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target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
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# 32+8+32 KB SRAM
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$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
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-work-area-size 0x92000 -work-area-backup 0
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# 16+2 KB M0 subsystem SRAM
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$_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
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-work-area-size 0x4800 -work-area-backup 0
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# Default to the Cortex-M4
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targets $_CHIPNAME.m4
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}
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if { ![using_hla] } {
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cortex_m reset_config vectreset
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}
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