tinyriscv-openocd/tcl
Robert Jordens 867bdb2e92 jtagspi: new protocol that includes transfer length
This commit contains a rewrite of the jtagspi protocol and covers both
changes in the jtagspi.c openocd driver and the bscan_spi
(xilinx_bscan_spi) proxy bitstreams. The changes are as follows:

1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
2. Insert alignment cycles for all BYPASSed TAPs:

  The previous logic was erroneous. The delay in clock cyles from a bit
  written to the jtag interface to a bit read by the jtag interface is:

  * The number of BYPASSed TAPs before this (jtagspi) tap
  * The length of the jtagspi data register (1)
  * The number of BYPASSed TAPs before this one.

  I.e. it is just the number of enabled TAPs. This also gets rid of the
  configuration parameter DR_LENGTH.

3. Use marker bit to start spi transfer

  If there are TAPs ahead of this one on the JTAG chain, and we are in
  DR-SHIFT, there will be old bits toggled through first before the first
  valid bit destined for the flash.
  This delays the begin of the JTAGSPI transaction until the first high bit.

4. New jtagspi protocol

  A JTAGSPI transfer now consists of:

  * an arbitrary number of 0 bits (from BYPASS registers in front of the
    JTAG2SPI DR)
  * a marker bit (1) indicating the start of the JTAG2SPI transaction
  * 32 bits (big endian) describing the length of the SPI transaction
  * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
  * an arbitrary number of cycles (to shift MISO/TDO data through
    subsequent BYPASS registers)

5. xilinx_bscan_spi: clean up, add ultrascale

This is tested on the following configurations:

* KC705: XC7K325T
* Sayma AMC: XCKU040
* Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
  adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
  Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
* Custom board with Lattice FPGA + XC7A35T
* CUstom board with 3x XCKU115-2FLVA1517E

Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 19:36:42 +00:00
..
board ftdi swd: disable SWD output pin during input 2018-01-13 11:37:13 +00:00
chip Fix a typo. 2013-07-07 13:00:59 +00:00
cpld jtagspi: new protocol that includes transfer length 2018-01-13 19:36:42 +00:00
cpu/arm Move TCL script files -- Step 2 of 2: 2009-05-27 06:49:24 +00:00
fpga tcl/fpga: add config file for Altera 10M50 FPGA (MAX10 family) 2016-08-14 02:05:18 +01:00
interface ftdi swd: disable SWD output pin during input 2018-01-13 11:37:13 +00:00
target Added config files for stm8l152 stm8s003 and stm8s105 2018-01-12 20:22:46 +00:00
test TCL scripts: replace "puts" with "echo" 2010-11-09 08:12:51 +01:00
tools tcl/board: add Linksys WAG200G config 2016-10-17 09:16:33 +01:00
bitsbytes.tcl TCL scripts: replace "puts" with "echo" 2010-11-09 08:12:51 +01:00
mem_helper.tcl tcl: add mrb command to mem_helper.tcl 2016-07-17 22:36:47 +01:00
memory.tcl target: add "phys" argument to mem2array, array2mem 2016-08-09 14:32:12 +01:00
mmr_helpers.tcl TCL scripts: replace "puts" with "echo" 2010-11-09 08:12:51 +01:00