91 lines
2.2 KiB
INI
91 lines
2.2 KiB
INI
#
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# target configuration for
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# Xilinx UltraScale+
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME uscale
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}
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#
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# DAP tap
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x5ba00477
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
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#
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# PS tap
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#
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if { [info exists PS_TAPID] } {
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set _PS_TAPID $PS_TAPID
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} else {
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set _PS_TAPID 0x04710093
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}
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set jtag_configured 0
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jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
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jtag configure $_CHIPNAME.ps -event setup {
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global _CHIPNAME
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global jtag_configured
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if { $jtag_configured == 0 } {
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# add the DAP tap to the chain
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# See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
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irscan $_CHIPNAME.ps 0x824
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drscan $_CHIPNAME.ps 32 0x00000003
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runtest 100
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# setup event will be re-entered through jtag arp_init
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# break the recursion
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set jtag_configured 1
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# re-initialized the jtag chain
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jtag arp_init
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}
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}
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set _TARGETNAME $_CHIPNAME.a53
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set _CTINAME $_CHIPNAME.cti
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set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
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set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
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set _cores 4
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for { set _core 0 } { $_core < $_cores } { incr _core } {
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cti create $_CTINAME.$_core -chain-position $_CHIPNAME.dap -ap-num 1 \
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-ctibase [lindex $CTIBASE $_core]
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set _command "target create $_TARGETNAME.$_core aarch64 -chain-position $_CHIPNAME.dap \
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-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
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if { $_core != 0 } {
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# non-boot core examination may fail
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set _command "$_command -defer-examine"
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set _smp_command "$_smp_command $_TARGETNAME.$_core"
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} else {
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# uncomment when "hawt" rtos is merged
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#set _command "$_command -rtos hawt"
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set _smp_command "target smp $_TARGETNAME.$_core"
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}
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eval $_command
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}
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eval $_smp_command
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targets $_TARGETNAME.0
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proc core_up { args } {
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global _TARGETNAME
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foreach { core } [set args] {
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$_TARGETNAME.$core arp_examine
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}
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}
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