92 lines
1.9 KiB
INI
92 lines
1.9 KiB
INI
# script for stm32l
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#
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# stm32 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 10kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x2800
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}
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# JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
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adapter_khz 100
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adapter_nsrst_delay 100
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if {$using_jtag} {
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jtag_ntrst_delay 100
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0038
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# Section 24.6.3
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set _CPUTAPID 0x4ba00477
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID] } {
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# FIXME this never gets used to override defaults...
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0038
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# Section 24.6.2
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set _BSTAPID 0x06416041
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}
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if {$using_jtag} {
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jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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proc stm32l_enable_HSI {} {
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# Enable HSI as clock source
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echo "STM32L: Enabling HSI"
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# Set HSION in RCC_CR
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mww 0x40023800 0x00000101
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# Set HSI as SYSCLK
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mww 0x40023808 0x00000001
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# Increase JTAG speed
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adapter_khz 2000
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}
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$_TARGETNAME configure -event reset-init {
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stm32l_enable_HSI
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}
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