117 lines
3.4 KiB
Tcl
117 lines
3.4 KiB
Tcl
# Generic init scripts for all ST SPEAr3xx family
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# http://www.st.com/spear
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#
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# Date: 2010-09-23
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# Author: Antonio Borneo <borneo.antonio@gmail.com>
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# Initialize internal clock
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# Default:
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# - Crystal = 24 MHz
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# - PLL1 = 332 MHz
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# - PLL2 = 332 MHz
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# - CPU_CLK = 332 MHz
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# - DDR_CLK = 332 MHz async
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# - HCLK = 166 MHz
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# - PCLK = 83 MHz
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proc sp3xx_clock_default {} {
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mww 0xfca00000 0x00000002 ;# set sysclk slow
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mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
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# DDRCORE disable to change frequency
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set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
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mww 0xfca8002c $val
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mww 0xfca8002c $val ;# Yes, write twice!
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# programming PLL1
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mww 0xfca8000c 0xa600010c ;# M=166 P=1 N=12
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mww 0xfca80008 0x00001c0a ;# power down
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mww 0xfca80008 0x00001c0e ;# enable
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mww 0xfca80008 0x00001c06 ;# strobe
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mww 0xfca80008 0x00001c0e
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while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
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# programming PLL2
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mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12
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mww 0xfca80014 0x00001c0a ;# power down
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mww 0xfca80014 0x00001c0e ;# enable
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mww 0xfca80014 0x00001c06 ;# strobe
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mww 0xfca80014 0x00001c0e
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while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
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mww 0xfca80028 0x00000082 ;# enable plltimeen
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mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
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mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
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while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
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# Select source of DDR clock
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#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
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mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
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# DDRCORE enable after change frequency
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mmw 0xfca8002c 0x20000000 0x00000000
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}
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proc sp3xx_common_init {} {
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mww 0xfca8002c 0xfffffff8 ;# enable clock of all peripherals
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mww 0xfca80038 0x00000000 ;# remove reset of all peripherals
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mww 0xfca80034 0x0000ffff ;# enable all RAS clocks
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mww 0xfca80040 0x00000000 ;# remove all RAS resets
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mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
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mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
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mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
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mww 0xfc000000 0x00000f5f
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# Initialize Bus Interconnection Matrix
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# All ports Round-Robin and lowest priority
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mww 0xfca8007c 0x80000007
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mww 0xfca80080 0x80000007
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mww 0xfca80084 0x80000007
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mww 0xfca80088 0x80000007
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mww 0xfca8008c 0x80000007
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mww 0xfca80090 0x80000007
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mww 0xfca80094 0x80000007
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mww 0xfca80098 0x80000007
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mww 0xfca8009c 0x80000007
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}
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# Specific init scripts for ST SPEAr310 system on chip
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proc sp310_init {} {
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mww 0xb4000008 0x00002ff4 ;# RAS function enable
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mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
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mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
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mww 0xfca80140 0x017bdef6
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}
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proc sp310_emi_init {} {
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# set EMI pad strength
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mmw 0xfca80134 0x0e000000 0x00000000
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mmw 0xfca80138 0x0e739ce7 0x00000000
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mmw 0xfca8013c 0x00039ce7 0x00000000
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# set safe EMI timing as in BootROM
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#mww 0x4f000000 0x0000000f ;# tAP_0_reg
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#mww 0x4f000004 0x00000000 ;# tSDP_0_reg
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#mww 0x4f000008 0x000000ff ;# tDPw_0_reg
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#mww 0x4f00000c 0x00000111 ;# tDPr_0_reg
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#mww 0x4f000010 0x00000002 ;# tDCS_0_reg
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# set fast EMI timing as in Linux
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mww 0x4f000000 0x00000010 ;# tAP_0_reg
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mww 0x4f000004 0x00000005 ;# tSDP_0_reg
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mww 0x4f000008 0x0000000a ;# tDPw_0_reg
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mww 0x4f00000c 0x0000000a ;# tDPr_0_reg
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mww 0x4f000010 0x00000005 ;# tDCS_0_re
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# 32bit wide, 8/16/32bit access
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mww 0x4f000014 0x0000000e ;# control_0_reg
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mww 0x4f000094 0x0000003f ;# ack_reg
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}
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