172 lines
5.4 KiB
INI
172 lines
5.4 KiB
INI
# The Atheros AR9331 is a highly integrated and cost effective
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# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
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# local area network (WLAN) AP and router platforms.
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#
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# Notes:
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# - MIPS Processor ID (PRId): 0x00019374
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# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
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# operating at up to 400 MHz
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# - External 16-bit DDR1, DDR2, or SDRAM memory interface
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# - TRST is not available.
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# - EJTAG PrRst signal is not supported
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# - RESET_L pin A72 on the SoC will reset internal JTAG logic.
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#
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# Pins related for debug and bootstrap:
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# Name Pin Description
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# JTAG
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# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG
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# JTAG_TDI GPIO6, (B46) Software configurable, default JTAG
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# JTAG_TDO GPIO7, (A54) Software configurable, default JTAG
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# JTAG_TMS GPIO8, (A52) Software configurable, default JTAG
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# Reset
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# RESET_L -, (A72) Input only
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# SYS_RST_L ???????? Output reset request or GPIO
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# Bootstrap
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# MEM_TYPE[1] GPIO28, (A74) 0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
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# MEM_TYPE[0] GPIO12, (A56)
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# FW_DOWNLOAD GPIO16, (A75) Used if BOOT_FROM_SPI = 0. 0 - boot from USB
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# 1 - boot from MDIO.
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# JTAG_MODE(JS) GPIO11, (B48) 0 - JTAG (Default); 1 - EJTAG
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# BOOT_FROM_SPI GPIO1, (A77) 0 - ROM boot; 1 - SPI boot
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# SEL_25M_40M GPIO0, (A78) 0 - 25MHz; 1 - 40MHz
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# UART
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# UART0_SOUT GPIO10, (A79)
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# UART0_SIN GPIO9, (B68)
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# Per default we need to use "none" variant to be able properly "reset init"
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# or "reset halt" the CPU.
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reset_config none srst_pulls_trst
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# For SRST based variant we still need proper timings.
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# For ETH part the reset should be asserted at least for 10ms
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# Since there is no other information let's take 100ms to be sure.
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adapter_nsrst_assert_width 100
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# according to the SoC documentation it should take at least 5ms from
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# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
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# to live.
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adapter_nsrst_delay 8
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $_CHIPNAME
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} else {
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set _CHIPNAME ar9331
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
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# provide watchdog helper.
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proc disable_watchdog { } {
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mww 0xb8060008 0x0
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}
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$_TARGETNAME configure -event halted { disable_watchdog }
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# Since PrRst is not supported and SRST will reset complete chip
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# with JTAG engine, we need to reset CPU from CPU itself.
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$_TARGETNAME configure -event reset-assert-pre {
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halt
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}
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$_TARGETNAME configure -event reset-assert {
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catch "mww 0xb806001C 0x01000000"
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}
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# To be able to trigger complete chip reset, in case JTAG is blocked
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# or CPU not responding, we still can use this helper.
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proc full_reset { } {
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reset_config srst_only
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reset
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halt
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reset_config none
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}
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proc disable_watchdog { } {
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;# disable watchdog
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mww 0xb8060008 0x0
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}
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$_TARGETNAME configure -event reset-end { disable_watchdog }
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# Section with helpers which can be used by boards
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proc ar9331_25mhz_pll_init {} {
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mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
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mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
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mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
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;# OUTDIV | REFDIV | DIV_INT
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mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
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;# (disabled?)
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mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
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mww 0xb8050008 0x00008000 ;# remove bypass;
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;# AHB_POST_DIV - ratio 2
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}
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proc ar9331_ddr1_init {} {
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mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
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mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb800000c 0x2 ;# Extended mode register value.
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;# default 0x2 - Reset to weak driver, DLL on
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mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x33 ;# mode reg: remove some bit?
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
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mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
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;# DQ[7:0], DQS_0
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mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
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;# DQ[15:8], DQS_1.
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mww 0xb8000018 0xff ;# DDR read and capture bit mask.
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;# Each bit represents a cycle of valid data.
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}
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proc ar9331_ddr2_init {} {
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mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
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mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
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mww 0xb800008c 0x00000a59
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mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle
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mww 0xb8000090 0x00000000
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mww 0xb8000010 0x00000010 ;# EMR2S update cycle
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mww 0xb8000094 0x00000000
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mww 0xb8000010 0x00000020 ;# EMR3S update cycle
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mww 0xb800000c 0x00000000
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mww 0xb8000010 0x00000002 ;# EMRS update cycle
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mww 0xb8000008 0x00000100
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mww 0xb8000010 0x00000001 ;# MRS update cycle
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mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle
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mww 0xb8000010 0x00000004
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mww 0xb8000010 0x00000004 ;# AUTO REFRESH cycle
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mww 0xb8000008 0x00000a33
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mww 0xb8000010 0x00000001 ;# MRS update cycle
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mww 0xb800000c 0x00000382
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mww 0xb8000010 0x00000002 ;# EMRS update cycle
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mww 0xb800000c 0x00000402
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mww 0xb8000010 0x00000002 ;# EMRS update cycle
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mww 0xb8000014 0x00004186 ;# DDR_REFRESH
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mww 0xb800001c 0x00000008 ;# DDR_TAP_CTRL0
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mww 0xb8000020 0x00000009 ;# DDR_TAP_CTRL1
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;# DDR read and capture bit mask.
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;# Each bit represents a cycle of valid data.
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;# 0xff: use 16-bit DDR
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mww 0xb8000018 0x000000ff
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}
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