83 lines
2.7 KiB
INI
83 lines
2.7 KiB
INI
#
|
|
# Texas Instruments DaVinci family: TMS320DM6446
|
|
#
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME dm6446
|
|
}
|
|
|
|
#
|
|
# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
|
|
# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
|
|
# Override by setting EMU01 to "-disable".
|
|
#
|
|
# Also note: when running without RTCK before the PLLs are set up, you
|
|
# may need to slow the JTAG clock down quite a lot (under 2 MHz).
|
|
#
|
|
source [find target/icepick.cfg]
|
|
set EMU01 "-enable"
|
|
#set EMU01 "-disable"
|
|
|
|
# Subsidiary TAP: unknown ... must enable via ICEpick
|
|
jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
|
|
jtag configure $_CHIPNAME.unknown -event tap-enable \
|
|
"icepick_c_tapenable $_CHIPNAME.jrc 3"
|
|
|
|
# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
|
|
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
|
|
jtag configure $_CHIPNAME.dsp -event tap-enable \
|
|
"icepick_c_tapenable $_CHIPNAME.jrc 2"
|
|
|
|
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
|
|
if { [info exists ETB_TAPID ] } {
|
|
set _ETB_TAPID $ETB_TAPID
|
|
} else {
|
|
set _ETB_TAPID 0x2b900f0f
|
|
}
|
|
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
|
|
-expected-id $_ETB_TAPID $EMU01
|
|
jtag configure $_CHIPNAME.etb -event tap-enable \
|
|
"icepick_c_tapenable $_CHIPNAME.jrc 1"
|
|
|
|
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
|
|
if { [info exists CPU_TAPID ] } {
|
|
set _CPU_TAPID $CPU_TAPID
|
|
} else {
|
|
set _CPU_TAPID 0x07926001
|
|
}
|
|
jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
|
|
-expected-id $_CPU_TAPID $EMU01
|
|
jtag configure $_CHIPNAME.arm -event tap-enable \
|
|
"icepick_c_tapenable $_CHIPNAME.jrc 0"
|
|
|
|
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
|
|
if { [info exists JRC_TAPID ] } {
|
|
set _JRC_TAPID $JRC_TAPID
|
|
} else {
|
|
set _JRC_TAPID 0x0b70002f
|
|
}
|
|
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
|
|
-expected-id $_JRC_TAPID
|
|
|
|
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
|
|
# and the ETB memory (4K) are other options, while trace is unused.
|
|
# Little-endian; use the OpenOCD default.
|
|
set _TARGETNAME $_CHIPNAME.arm
|
|
|
|
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
|
|
$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
|
|
|
|
# be absolutely certain the JTAG clock will work with the worst-case
|
|
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
|
|
# on the PLL and starts using it. OK to speed up after clock setup.
|
|
jtag_rclk 1500
|
|
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
|
|
|
|
arm7_9 fast_memory_access enable
|
|
arm7_9 dcc_downloads enable
|
|
|
|
# trace setup
|
|
etm config $_TARGETNAME 16 normal full etb
|
|
etb config $_TARGETNAME $_CHIPNAME.etb
|