108 lines
3.2 KiB
INI
108 lines
3.2 KiB
INI
#xscale ixp42x CPU
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME ixp42x
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a bigendian
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set _ENDIAN big
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x19274013
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}
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set _CPUTAPID2 0x19275013
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set _CPUTAPID3 0x19277013
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set _CPUTAPID4 0x29274013
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set _CPUTAPID5 0x29275013
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set _CPUTAPID6 0x29277013
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jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
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# register constants for IXP42x SDRAM controller
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global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
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global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
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set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000
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set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001
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global IXP42x_SDRAM_CL3
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global IXP42x_SDRAM_CL2
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set IXP42x_SDRAM_CL3 0x0008
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set IXP42x_SDRAM_CL2 0x0000
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global IXP42x_SDRAM_8MB_2Mx32_1BANK
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global IXP42x_SDRAM_16MB_2Mx32_2BANK
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global IXP42x_SDRAM_16MB_4Mx16_1BANK
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global IXP42x_SDRAM_32MB_4Mx16_2BANK
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global IXP42x_SDRAM_32MB_8Mx16_1BANK
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global IXP42x_SDRAM_64MB_8Mx16_2BANK
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global IXP42x_SDRAM_64MB_16Mx16_1BANK
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global IXP42x_SDRAM_128MB_16Mx16_2BANK
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global IXP42x_SDRAM_128MB_32Mx16_1BANK
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global IXP42x_SDRAM_256MB_32Mx16_2BANK
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set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030
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set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031
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set IXP42x_SDRAM_16MB_4Mx16_1BANK 0x0032
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set IXP42x_SDRAM_32MB_4Mx16_2BANK 0x0033
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set IXP42x_SDRAM_32MB_8Mx16_1BANK 0x0010
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set IXP42x_SDRAM_64MB_8Mx16_2BANK 0x0011
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set IXP42x_SDRAM_64MB_16Mx16_1BANK 0x0012
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set IXP42x_SDRAM_128MB_16Mx16_2BANK 0x0013
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set IXP42x_SDRAM_128MB_32Mx16_1BANK 0x0014
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set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015
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# helper function to init SDRAM on IXP42x.
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# SDRAM_CFG: one of IXP42X_SDRAM_xxx
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# REFRESH: refresh counter reload value (integer)
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# CASLAT: 2 or 3
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proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
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switch $CASLAT {
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2 {
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set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ]
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set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
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}
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3 {
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set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ]
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set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
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}
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default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
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}
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echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
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mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
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mww 0xCC000004 0 ;# disable refresh
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mww 0xCC000008 3 ;# NOP
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sleep 100
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mww 0xCC000004 $REFRESH ;# set refresh counter
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mww 0xCC000008 2 ;# Precharge All Banks
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sleep 100
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 4 ;# Auto Refresh
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mww 0xCC000008 $CASCMD ;# Mode Select CL2/CL3
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}
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proc ixp42x_set_bigendian { } {
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reg XSCALE_CTRL 0xF8
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}
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