Darius Rad 00b591a09a Add 'riscv set_ir' command to set IR value for JTAG registers. ... This allows using different TAP addresses, for example, if using BSCANE2 primitives on a Xilinx FPGA.		2019-01-09 17:20:39 -05:00
..
flash	From upstream (#331)	2018-11-19 12:46:40 -08:00
helper	Merge branch 'riscv' into notice_reset	2018-04-30 13:36:06 -07:00
jtag	From upstream (#331)	2018-11-19 12:46:40 -08:00
pld	Convert to non-recursive make	2016-12-08 16:23:10 +00:00
rtos	From upstream (#331)	2018-11-19 12:46:40 -08:00
server	From upstream (#331)	2018-11-19 12:46:40 -08:00
svf	svf: improve robustness when processing invalid SVF files	2018-03-13 08:41:21 +00:00
target	Add 'riscv set_ir' command to set IR value for JTAG registers.	2019-01-09 17:20:39 -05:00
transport	configure: disable all drivers when zy1000 is enabled	2018-05-08 15:21:49 -07:00
xsvf	Convert to non-recursive make	2016-12-08 16:23:10 +00:00
Makefile.am	Convert to non-recursive make	2016-12-08 16:23:10 +00:00
hello.c	Remove FSF address from GPL notices	2016-05-24 22:30:01 +01:00
hello.h	Make #include guard naming consistent	2016-05-24 22:30:55 +01:00
main.c	Remove FSF address from GPL notices	2016-05-24 22:30:01 +01:00
openocd.c	armv8: valgrind memleak fixes	2018-05-08 15:21:49 -07:00
openocd.h	Make #include guard naming consistent	2016-05-24 22:30:55 +01:00