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tinyriscv-openocd
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  • 0463f8d773 README: add linux build steps tinyriscv liangkangnan 2021-11-11 09:56:11 +0800
  • 916fcb01cb loader: add tinyriscv liangkangnan 2021-11-11 09:55:02 +0800
  • 9bbbaf9bad add tinyriscv_program command liangkangnan 2021-11-11 09:54:00 +0800
  • e5a97681ea target: add load_bin command liangkangnan 2021-05-31 11:48:54 +0800
  • 76b7bb357b add README.md liangkangnan 2020-06-13 13:29:05 +0800
  • 26b7b3c917 README: update liangkangnan 2020-06-13 13:23:26 +0800
  • 66f480322a add tinyriscv manu code liangkangnan 2020-06-13 13:14:10 +0800
  • e2b555e287 git ignore release dir liangkangnan 2020-06-13 13:13:19 +0800
  • a610f377c9 add release.sh liangkangnan 2020-06-13 13:12:30 +0800
  • 65ff1f1dd2 add rebuild.sh liangkangnan 2020-06-13 13:11:44 +0800
  • c94bf74155 README: update Blue Liang 2020-06-12 19:06:22 +0800
  • 3cc6fe00af README: add build steps Blue Liang 2020-06-12 19:01:20 +0800
  • eefff456ca submodule: use gitee jimtcl repo liangkangnan 2020-06-11 23:31:41 +0800
  • 97fb3f4bd4
         Add RISC-V to README. (#482) riscv Tim Newsome 2020-06-09 12:49:37 -0700
  • 95a8cd9b5d
         Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issu… (#479) Tommy Murphy 2020-05-26 18:33:30 +0100
  • 4f9e2d7171
         Fix semihosting for multicore targets (#478) Tim Newsome 2020-05-19 10:34:36 -0700
  • 1524487a13
         Speed up SBA block reads roughly 2x. (#477) Tim Newsome 2020-05-18 14:43:41 -0700
  • 62af8d3c10
         Improvements for the HiFive1 revB (#476) Alistair Francis 2020-05-15 11:31:32 -0700
  • fcdb5d64ec
         Make mem2array work with 64-bit addresses. (#475) Tim Newsome 2020-05-14 10:19:24 -0700
  • 0c3e50a06a
         Don't cache PC, but do cache DPC. (#473) Tim Newsome 2020-05-06 08:43:59 -0700
  • 55dd7e83ca
         Add awareness of halt group cause. (#472) Tim Newsome 2020-05-06 08:42:38 -0700
  • e6e281197f
         Cache accesses through riscv_[sg]et_register. (#467) Tim Newsome 2020-04-21 14:58:59 -0700
  • 397d5be64b Don't read registers that we know don't exist. regcache Tim Newsome 2020-04-21 10:48:03 -0700
  • bd7d75d4b9 Fix whitespace. Tim Newsome 2020-04-20 15:22:01 -0700
  • eaabf76fde Cache accesses through riscv_[sg]et_register. Tim Newsome 2020-04-20 15:09:08 -0700
  • 2e9aad8914
         Don't propagate failure to read satp in riscv_mmu() (#466) Tim Newsome 2020-04-13 12:53:26 -0700
  • 464407cfd2
         Expose FPRs as single and double for F and D. (#465) Tim Newsome 2020-04-10 13:32:12 -0700
  • cbb15587dc
         Document default values for some config options. (#461) Tim Newsome 2020-03-27 11:21:02 -0700
  • 3967f48843
         Fix some clang static checker complaints. (#464) Tim Newsome 2020-03-27 11:20:48 -0700
  • 60eccb2967
         Use the correct thread for memory accesses. (#459) Tim Newsome 2020-03-26 09:46:32 -0700
  • 5b2426a4b2
         Deal with vlenb being unreadable. (#458) Tim Newsome 2020-03-26 09:08:56 -0700
  • 548790fefc
         Add support for HiFive1 RevB board (#456) Jonathan Tinkham 2020-03-19 10:31:05 -0600
  • f6f30fb148
         Update to 1.11 privileged spec. (#455) Tim Newsome 2020-03-18 12:24:22 -0700
  • 54e5d2533c
         helper: skip including sys/sysctl.h on Linux (#450) Tim Newsome 2020-03-05 12:13:33 -0800
  • 1ae21b3874
         Fix address translation when high bits are set. (#453) Tim Newsome 2020-03-05 11:33:51 -0800
  • 1449af5bdb
         Give control over dcsr.ebreak[msu] bits. (#451) Tim Newsome 2020-02-20 13:58:15 -0800
  • 95462a8a35
         Add support for vector register access (#448) Tim Newsome 2020-02-14 14:54:05 -0800
  • 7cb8843794
         Update the current thread when gdb requests a step. (#444) Tim Newsome 2020-01-31 12:56:46 -0800
  • 2f456abd55
         Complain about debug version before authentication. (#441) Tim Newsome 2020-01-27 16:07:08 -0800
  • 23a0ce22cf Reading v* registers appears to work. vector2 Tim Newsome 2020-01-24 14:10:04 -0800
  • 9e80ab1f85 WIP Tim Newsome 2020-01-13 15:11:35 -0800
  • 69e6891434
         Handle DMI busy in sba write. (#437) Tim Newsome 2020-01-13 15:10:43 -0800
  • fcea4f79ba Don't issue extra FENCE+FENCE.i for the current hart. (#439) Jan Matyas 2020-01-10 21:29:10 +0100
  • 8b8db033ee
         Upcast mask value to work with 64-bit physical (#436) Tim Newsome 2020-01-06 16:57:15 -0800
  • 2c3f099b73 Fix bugs. Do not touch SATP if there is no MMU. (#435) Hsiangkai 2020-01-01 03:27:22 +0800
  • 06c596e19f Rename ERROR_BUSY to ERROR_TARGET_BUSY. busy Tim Newsome 2019-12-18 14:19:18 -0800
  • 8a9df230ad Fix style. Tim Newsome 2019-12-18 14:11:20 -0800
  • 4fa9f61739 Deal with a case where DMI read returns busy. Tim Newsome 2019-12-18 14:02:32 -0800
  • 9886f77374 riscv: translate virtual address to physical address. (#425) Hsiangkai 2019-12-11 04:18:03 +0800
  • aec5cca15b Increase maximum number of harts (#429) bluew 2019-12-06 02:22:12 +0100
  • 780d8e4d3e
         Remove unused data structure. (#431) Tim Newsome 2019-12-04 16:23:22 -0800
  • 50d0c2f67c
         Warn about using `-rtos riscv`. (#430) Tim Newsome 2019-12-04 12:22:49 -0800
  • e03dd199e0 Fixed write_memory_progbuf() on RV64. (#426) Jan Matyas 2019-11-28 00:24:25 +0100
  • de00906ebd
         Fix memory access on some targets. (#428) Tim Newsome 2019-11-22 11:37:46 -0800
  • 739d16d503 Fix: Take into account progbuf writability. (#424) Jan Matyas 2019-11-20 21:00:00 +0100
  • 59019f103c Fix memory access on some targets. mem64 Tim Newsome 2019-11-20 11:34:05 -0800
  • e944de422e
         fespi: Properly support large flash devices (#421) Tim Newsome 2019-11-15 12:50:08 -0800
  • b7bd3f8d47 BSCAN batch fix (#422) Greg Savin 2019-11-12 09:00:35 -0800
  • c1b79a85bb Whenever bscan mode is entered, reset the variable that tracks whether we are certain that USER4 has already been selected into IR. bscan_optimization Greg Savin 2019-11-05 13:44:25 -0800
  • 1e3c2bdda4 Fix for formatting issues Greg Savin 2019-11-04 16:31:25 -0800
  • 32413fee3e For BSCAN tunneling, USER4 only needs to be scanned into IR once, and then left there for the remainder of the session. Greg Savin 2019-11-04 16:14:10 -0800
  • f93ede5401
         Add support for 64-bit memory reads/writes (#419) Tim Newsome 2019-11-04 11:04:30 -0800
  • 20804cb4d2
         pmpcfg[13] only exist on RV32. (#416) Tim Newsome 2019-10-23 11:37:51 -0700
  • 0409bf9b24
         Merge pull request #417 from riscv/heterogeneous Tim Newsome 2019-10-14 12:18:52 -0700
  • 885260505a Combine SMP group registers into one list for gdb Tim Newsome 2019-10-11 15:51:35 -0700
  • 91d00468b6
         Merge pull request #413 from riscv/compliance Tim Newsome 2019-10-09 11:41:29 -0700
  • 3b4fcf471f The compliance test is poorly supported. Tim Newsome 2019-10-03 16:36:24 -0700
  • 7c82a7b9d5
         Merge pull request #411 from riscv/from_upstream Tim Newsome 2019-09-30 13:23:19 -0700
  • f9bc528478 Fix filterdiff line. Tim Newsome 2019-09-30 12:47:34 -0700
  • 1107dc7e3f Fix the build. Tim Newsome 2019-09-27 16:35:03 -0700
  • 53b87ddfc5 Update libjaylink. Tim Newsome 2019-09-27 12:12:32 -0700
  • 9aac179cf2 Merge branch 'master' into from_upstream Tim Newsome 2019-09-27 12:07:00 -0700
  • bbdc28e0f5
         Use more idiomatic assembly for flash code. (#410) Tim Newsome 2019-09-25 11:51:07 -0700
  • 20fc862b15 Perform SBA writes with batch transactions for improved performance. (#405) darius-bluespec 2019-09-25 00:49:25 +0000
  • 3110092720 src/jtag/aice: Fix obviously incorrect bit op. Seth LaForge 2019-09-12 09:18:45 -0700
  • 31a3324b68 helper/command: clear errno before calling parser Christopher Head 2019-09-09 13:52:51 -0700
  • 181d594205 flash/nor/tcl: Fix usage of 'flash erase_sector' command Marc Schink 2019-09-11 11:08:29 +0200
  • bf1e201336
         The stack is relative to the program. (#409) Tim Newsome 2019-09-23 15:51:17 -0700
  • 85a460d5a3 tcl/board: Add Rigado BMD-300 Evaluation Kit Marc Schink 2019-06-06 13:14:29 +0200
  • 101345270b esirisc_flash: Rename PAGE_SIZE to FLASH_PAGE_SIZE Khem Raj 2019-05-20 23:24:26 -0700
  • c5bb7fb230
         Add TCK padding in the OSCAN1 reset/online/activate sequence. (#406) Greg Savin 2019-09-13 12:50:36 -0700
  • 11e6127401
         Display IDCODE in message about it not existing. (#404) Tim Newsome 2019-09-11 10:48:18 -0700
  • 274be9587f
         Fix flashing HiFive Unleashed (#402) Tim Newsome 2019-09-09 12:01:17 -0700
  • 09eb941cb8 flash/nor/stm32h7x: remove unused 'pages_per_sector' from stm32h7x_part_info Tarek BOCHKATI 2019-08-27 14:44:49 +0200
  • 5b06b88af8 flash/nor/stm32h7x: remove flash size information from device name Tarek BOCHKATI 2019-08-27 14:18:21 +0200
  • 5a235226f0 flash/nor: flash driver for Synwit SWM050 MCUs Caleb Szalacinski 2019-08-19 17:45:27 -0500
  • 642a9310ca target/dsp563xx: dsp563xx restore reg support Han Hartgers 2019-06-17 20:39:31 +0200
  • 844c82934e src/flash/nand: Fix some operator precedence bugs. Seth LaForge 2019-08-19 10:40:07 -0700
  • 24d59cfb90
         Update jep106.inc by running the script. (#400) Tim Newsome 2019-09-07 11:38:15 -0700
  • 8207cf8d94 Changing ERROR to DEBUG for non existing registers debug-log-reg-failure cgsfv 2019-08-30 12:00:44 -0700
  • 30b93b8661
         Revert part of da12994 to fix ^C being eaten. (#397) Tim Newsome 2019-08-28 10:57:23 -0700
  • 0819541366 gdb_server, rtos: Fine-grained RTOS register access Tim Newsome 2019-04-08 16:42:48 -0700
  • 5173ddf75e
         Use only one hart to run algorithm. (#396) Tim Newsome 2019-08-26 11:24:29 -0700
  • cd7eea6d76 Adds support for RISCV Access Memory Abstract Commands (#394) dave-estes-syzexion 2019-08-19 17:03:20 -0400
  • efce094b40
         Don't fake step for hwthread rtos. (#393) Tim Newsome 2019-08-14 11:56:44 -0700
  • 16496488d1 flash/nor/core: fix some minor typo Tarek BOCHKATI 2019-07-16 17:14:50 +0200
  • 320f7517c4 contrib/rpc_examples: Adapt to new command line handling Marc Schink 2019-07-01 14:34:30 +0200
  • 7a93c9e087 mflash: Remove this broken flash driver Andreas Fritiofson 2019-06-19 10:31:05 +0200
  • 7eaf60f1b5
         Properly detect errors in SBA reads. (#392) Tim Newsome 2019-07-26 11:08:35 -0700
  • 239a515a9c Access memory through the scope of current privilege level (#386) Nils Wistoff 2019-07-18 22:15:28 +0200