Fix for LOG format specifiers, this is a superset of those
exposed by the arm-none-eabi build.
Add 0x prefix for all values printed in hex.
Add LOG messages for error cases when enabling or disabling
paging.
Change-Id: I070c556e0ad31204231a2b572e7b93af22a9bc61
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/2149
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The spifi_init_code blob is calling the spifi_init() function from the ROM.
This ROM function is making use of the stack. So if the stack pointer is
invalid, trying to execute this code leads to a double fault and the
target_run_algorithm() call return with an error.
This patch simply ensure that the stack pointer is properly setup before
calling the spifi_init() ROM function.
Change-Id: I42a2163cfc2c6dfe5ada97ae8eb2bb6d2e283ff7
Signed-off-by: Aurelien Jacobs <aurel@gnuage.org>
Reviewed-on: http://openocd.zylin.com/1836
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Old version of the code had several problems, among them are:
* Located in a generic ADI source file instead of some Kinetis
specific location
* Incorrect MCU detection code that would read generic ARM ID
registers
* Presence of SRST line was mandatory
* There didn't seem to be any place where after SRST line assertion
it would be de-asserted.
* Reset was asserted after waiting for "Flash Controller Ready" bit
to be set, which contradicts official programming guide AN4835
* Mass erase algorithm implemented by that code was very strange:
** After mass erase was initiated instead of just polling for the
state of "Mass Erase Acknowledged" bit the code would repeatedly
initiate mass erase AND poll the state of the "Mass Erase
Acknowledged"
** Instead of just polling for the state of "Flash Mass Erase in
Progress"(bit 0 in Control register) to wait for the end of the
mass erase operation the code would: write 0 to Control
register, read out Status register ignoring the result and then
read Control register again and see if it is zero.
* dap_syssec_kinetis_mdmap assumed that previously selected(before
it was called) AP was 0.
This commit moves all of the code to kinetis flash driver and
introduces three new commands:
o "kinetis mdm check_security" -- the intent of that function is to be used as
'examine-end' hook for any Kinetis target that has that kind of
JTAG/SWD security mechanism.
o "kinetis mdm mass_erase"" -- This function removes secure status from
MCU be performing special version of flash mass erase.
o "kinetis mdm test_securing" -- Function that allows to test securing
fucntionality. All it does is erase the page with flash security settings thus
making MCU 'secured'.
New version of the code implements the algorithms specified in AN4835
"Production Flash Programming Best Practices for Kinetis K-
and L-series MCUs", specifically sections 4.1.1 and 4.2.1.
It also adds KL26 MCU to the list of devices for which this security
check is performed. Implementing that algorithm also allowed to simplify
mass command in kinetis driver, since we no longer need to write security
bytes. The result that the old version of mass erase code can now be
acheived using 'kinetis mdm mass_erase'
Tested on accidentally locked FRDM-KL26Z with KL26 Kinetis MCU.
Change-Id: Ic085195edfd963dda9d3d4d8acd1e40cc366b16b
Signed-off-by: Andrey Smrinov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2034
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is only the basic code proposed for mips32_pracc_exec() function.
It checks every pracc address against the expected address when
reading (instruction fetch).
The code expects to start at PRACC_TEXT and any subsequent read address
is obtained by adding 4 to the previous one.
After shifting out all the instructions the code executes a final check.
It checks now for the first pass trough PRACC_TEXT and shift out
only NOP instructions.
A mips core does not need an additional NOP and after the first check
it exits if there is no store access pending.
After shifting out one NOP the core must be reading at pracc text or the
code exits with error.
The code continues shifting out NOPs until all store accesses have
been performed.
After shifting out 10 NOPs it exits with error.
No assumption is made about the number of store instruction shifted out or
the ordering of the store accesses. It only checks that the number of
store accesses is the same as the number of store instructions at dmseg
after execution.
mips32_pracc_read_ctrl_addr() and mips32_pracc_finish() are added to
simpify a bit the code. Fields pa_ctrl and pa_addr are added
in ejtag_info for storing values of pracc control and address.
Change-Id: If6322d5c8cbeadcd4acd3972c0f72c8490f53c34
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1827
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This is the first patch intended to make a more precise pracc check
when running in legacy mode (code executed by mips32_pracc_exec()).
It only makes some cleanups, mostly due to unnecessary code.
With the last cache optimizations for processor access (pa for short)
all the pracc functions generate the code following some rules that
make pa more easily to check:
There are no load instructions from dmseg. All the read pas are
instruction fetches. PARAM_IN related stuff is not needed.
Registers are restored either from COP0 DeSave or from ejtag
info fields. PRACC_STACK related stuff is not needed any more.
The code starts execution at PRACC_TEXT and there are no branch or jump
instruction in the code, apart from the last jump to PRACC_TEXT.
The fetch address is ever known.
For every store instruction to dmseg the function code sets
the address of the write/store pa.
The address of every store pa is known.
Current code ends execution when reading a second pass through PRACC_TEXT.
This approach has same inconveniences:
If the code starts in the delay slot of a jump it makes a jump
to PRACC_TEXT after executing the first instruction. A second pass
through PRACC_TEXt is read and the function exits without any warning.
This seems to occur sometimes when a 24kc core is halted in the delay
slot of a branch.
If a debug mode exception is triggered during the execution of a
function the core restarts execution at PRACC_TEXT. Again the function
exits without any warning.
If for whatever reason the core starts fetching at an unexpected
address the code now sends a jump instruction to PRACC_TEXT, but due
to the delay slot the core continues fetching at whatever address + 4
and a second jump instruction will be send for execution. The result
of a jump instruction in the delay slot of another jump is
UNPREDICTABLE. It may work as expected (ar7241), or let the core in
the delay slot of a jump to PRACC_TEXT for example. This means the
function called next may also fail (pic32mx).
Change-Id: I9516a5146ee9c8c694d741331edc7daec9bde4e3
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1825
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Near all pracc functions store $15 in DeSave and
restore it when exiting.
There is no need to save it, if mips32_pracc_read_regs()
save this register in Desave when entering debug mode.
mips32_pracc_write_regs() needs to update it when
exiting debug mode.
Other pracc functions must not modify DeSave.
The jump code in the fastdata transfer function needs also
some little modifications.
Remark:
Like in current code the user can read/modify $15
with the cp0 31 commands.
Change-Id: I5b7dfc1b6169da846f5d2dd3ad4209a9da2c3fad
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1565
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Currently the code is loaded calling mips32_pracc_write_mem_generic().
Cache synchronization is not performed.
If configured as write back cache there is no chance to execute the
handler. If configured as write through cache and the cache
lines written to are not cache resident (I-side cache miss) may work.
The patch makes possible to execute the handler in a cached active
memory segment (mainly from KSEG0), but nothing else. The data
is still loaded without performing cache synchronization, code loaded
may not be executable.
Performance may not be faster. At start, for example, the code resides in
main memory, not in cache, and the core must transfer code from
memory. We can really modify the code to force a wait for the first
transfer like we do with start and end addresses, making sure the code
is cache resident for the rest of the queued transfers.
This can also may happen if we execute code (greater than the I cache size)
and the handler code is evicted from the cache.
Code tested on ar7241.
Change-Id: Iffdb4dae108b872fef0e7bacc5ea99649cdc1630
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1564
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Currently the functions mips32_checksum_memory() and mips32_blank_check_memory()
load the code word by word.
The bug in cache code is a good reason for doing so.
If there is no other reason we can load the code as a buffer to save time.
mips_m4k_write_memory() expect a buffer in target endianness, this is done by
target_buffer_set_u32_array().
Cleaned up exit code.
Tested on ar7241 big endian and pic32mx little endian with verify_image.
Flash erase check only tested in pic32mx.
Change-Id: Ib63ed98732b2e23b058e7349a0a57934b7604905
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1562
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Follows the the same rules of optimization used by all pracc functions.
Solves some bugs in previous code and adds support for write through caches.
Change-Id: If88c6738ca8c8197f327f22b766120a24f71b567
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1557
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This is a post-release version but hopefully some fixes that went in
are worth it; also the changes here make OpenOCD compatible with stock
0.75 version if a distro maintainer decides to use it.
Change-Id: I7ad1814c7c4868198475cdca4750c3d0ee4f5f8b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2121
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Only send the new I/O state for the bytes that changed.
Change-Id: I930edc9518e6019331e68e4756acc5e92dda25a4
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1999
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Added SVF_BUF_LOG macro to properly print the hex buffer of parsed
string for SIR, SDR, TDI, TDO and MASK. The original debug and error
logs with respect to printing real values were misleading and also
had endianess issues. All the bits are printed now instead of just
u32 values.
Change-Id: Ie89902403bdb61ff458418446c2ca1253ea2a63f
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1964
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
As exposed by arm-none-eabi build, fix the wrong modifiers.
Change-Id: Ia6ce7c5c1d40e95059525c3e5d81b752df2fea7c
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2122
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paging checking and disabling wasn't present for IO r/w,
so the commands were successful only when paging wasn't
enabled (e.g. EFI boot phase).
Change-Id: I41366c0fadff3ea1eb8a153291f20a46cd9ddec1
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/2118
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
On larger FPGAs the default buffer size is not nearly enough;
automatically reallocate it as needed.
Change-Id: Ic8071e8cceddeef897ce76996c029250fd22662b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2099
Tested-by: jenkins
Reviewed-by: Kenneth Lorthioir <ibelimb@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The TI TMS470 and TMS570 series of processors are BE-32 processors,
despite BE-32 not being supported by ARM in the Cortex-R4 core. TI
hacked in BE-32 support, which requires odd swizzling in OpenOCD to
make memory reads and writes function correctly. In particular,
without this change, OpenOCD word reads and writes had the bytes
reversed, and halfword and byte packed reads were reading garbage.
In my testing, this change fixes these problems.
Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/2064
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Since c6216201b2 gdb target description
generation support is enabled by default and it counts on checking
"feature" pointer in reg_list. Both mips32 and dsp563xx neither used
calloc nor explicitly set feature (as it was a newly introduced struct
field).
This patch changes all targets to use calloc for consistency.
Change-Id: I9eceadef8b04aacb108e24ae23cb51ca3009586f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2102
Tested-by: jenkins
Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Different *nix systems use different constants, so sizeof should be
used instead. This fixes the build on OS X (as sun_path length is
hardcoded to 104 on Darwin).
Change-Id: I1df611383dedcfc6d153ec59b453a895c7d84e94
Reported-by: Xiaofan Chen <xiaofanc@gmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2095
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
According to the "Arm Arch Ref Manual ARMv7-a and ARMv7-R edition" the
CPSR encoding for Monitor mode is 0b10110 (22) not 0b11010 (26) as is
currently used.
Change-Id: I73373a0029a81abc92febf518b88bf0dd4dec1fa
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2081
Reviewed-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Tested-by: jenkins
Reviewed-by: Younes REGAIEG <y.regaieg@gmail.com>
Reviewed-by: Tim Sander <tim@krieglstein.org>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
If gdb was disconnected by the moment the target entered halted state,
update_halt_gdb would segfault.
Change-Id: I67477e9199c1df097be83a49e38602f975c083f5
Reported-by: Younes REGAIEG <younes.regaieg@imag.fr>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2098
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Those are breaking the build with clang 3.4 (current default compiler
on OS X 10.9.2).
Change-Id: I9f2fbfbb6d544498cb8d6a62565e4ebe7223e784
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2077
Tested-by: jenkins
Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
Apparently this helper was never actually used, and current clang
produces an unused const variable warning, so it's breaking the build.
Change-Id: Ib088bef5e9c0a48942c1d417d46f738469ee7e28
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2076
Tested-by: jenkins
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
Some fixes to 'samd_protect' including:
- Fix a bug in which the value of 'set' parameter passed into the
function was ignored so it was impossible to remove flash
protection once it was set.
- Check the protection status of the sector via 'is_protected'
field of the corresponding 'flash_sector' structure to see if
any actual HW manipulations needs to be done.
- Change the way the errors during protection activation are
handled. Now even in the case of error in the middle of
protecting a number of sectors the subroutine would still update
the state of the sector protection in sectors array so as to
avoid cases where openocd thinks that the sector is not protected
while it actually is.
Change-Id: I4cc6445a98ec13bdd94c89f0711c17840738a215
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2027
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Bail early if trying to erase protected sector and also do not double-erase already
erased sectors.
Change-Id: Ic2d39af48c3b8e10e78d52dd978b9bc01f671c6a
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2026
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Bail early if trying to write to protected sector also mark the sector
we are writing to as dirty.
Change-Id: I892f83461792e1cc2dcccade7aa65717831a6805
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2025
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Remove 'first' and 'last' checks in 'samd_protect' since those
parameters are checked in 'handle_flash_erase_command'.
Change-Id: I30e5598a9ab656d81055f26cc63e291377605300
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2024
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This introduces a new global Tcl procedure that is run just after
init_targets and before init_boards.
Its default behaviour is to assign gdb-flash-erase-start and
gdb-flash-write-end to reasonable defaults.
The rationale for doing "reset init" before gdb erases and flashes
memory is that all flash drivers are written in assumption that they
can safely be used only after chip reset (plus chip-specific
configuration in the init handler if any). The need to use "reset
halt" after flashing is because a user expects running firmware after
loading to be the same as running it from power-on-reset.
Change-Id: I9ddc4047611904ca4ca779b73376d2739611948a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2062
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
COMMAND_PARSE_NUMBER may return, thus any memory allocated may not be
freed, simple reorder fixes the issue.
Change-Id: I0ce444a5b032f5c49b6d33a03a8c0b71cad49c8c
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2065
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
GPL requires providing sources for any derived work. I do not see any
reason to not include the xscale stuff into release tarballs.
Wildcard matching is used because plain directory name matches
implicit rule for executables and xscale.c built is errorneously
attempted, and directory name with a slash duplicates a directory
(xscale/xscale) in dist.
Change-Id: Ie0266470dcb97be87a09ba2dda9b3957f7cbc2fa
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1911
Tested-by: jenkins
Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
GPL requires providing sources for any derived work. I do not see any
reason to not include the rlink stuff into release tarballs.
Change-Id: I686ab88994030312aca5bdfe731a72f10803b5c3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1907
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Seems that when xml register support was added the rtos code was not
updated to match. This then caused gdb to return the following error when
rtos support was enabled - "Remote 'g' packet reply is too long".
Change-Id: I7429c4b1efed120e2e690678d55f3d6e87ee1ff1
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2054
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
nRF51 doesn't have any sort of flash page cache so we need to write
all of the data on the word-by-word basis and poll for "Flash Ready"
bit each time.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: I8caffbf69ebf9a69915724704ddbe270d1bb8d92
Reviewed-on: http://openocd.zylin.com/2050
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
SoftDevice stack ihex binary, provided by Nordic expects being able to
write data necessary for its correct operation at the adresses inside UICR.
This patch exposes UICR region of flash as a second bank on the MCU to
facilitate that.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: Idbc140b8de027f60655f78043877b7c054eb06f9
Reviewed-on: http://openocd.zylin.com/2013
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Unfortunately due to my oversight, the original version of the
nrf51_probe function contained useless code that read the contents of
DEVICEID[0] an DEVICEID[1] registers and did nothing about it(those
registers had nothing to do with the device type information anyway).
This commit fixes that code by changing its behavior to read the HWID
field of CONFIGID register and looking up the corresponding device
information in the know devices table. This information is useful
when choosing the versions of SDK and SoftDevice for the chip
using "nRF51822 compatibility matrix".
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: Ibd80b35460df4278e86e0c2500b7dcc876eec10c
Reviewed-on: http://openocd.zylin.com/2012
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Ignoring the value parameter in that function makes its code rather
misleading. Also the only caller of it, armv7m_restore_context already
does the whole "buf_get_u32" conversion business, so using
'value' also removes the waste of doing the conversion twice.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: I515979c314d9b59ee1065c55b5bb5747c7e93f01
Reviewed-on: http://openocd.zylin.com/2057
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser
Ivan De Cesaris
Aurelien Jacobs
Andrey Smirnov
Salvador Arroyo
Andreas Fritiofson
Kamal Dasu
Spencer Oliver
Seth LaForge
Tim Sander
Karl Hammar