zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
9,143 Commits
46 Branches
9 Tags
21 MiB
Commit Graph

1 Commits (bd7d75d4b936dcefc24ea8fb1314876bb5bd6953)

Author SHA1 Message Date
Marek Vasut 82e3a0e7cf tcl/target: Add Renesas RZ/A1H target 
Add configuration for the Renesas RZ/A1H target.
This is an SoC with one Cortex A9 ARMv7a core and
up to 10 MiB of on-SoC SRAM.

Change-Id: I20fd54b385fe1ba1cc325451c3fdfa3a835d4884
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5141
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
 2019-05-20 11:16:54 +01:00