Commit Graph

7379 Commits (bcf2a16b0d0d186fdfb371ff4e8009251626ee22)

Author SHA1 Message Date
Palmer Dabbelt bcf2a16b0d Shim back in some old interfaces for now 2017-05-11 10:41:13 -07:00
Palmer Dabbelt 563f6acc3c Allow all harts to be reset 2017-05-09 13:33:20 -07:00
Megan Wachs fa8d7adf33 Avoid accessing null target->reg_cache
GDB might request registers even if target was not successfully initialized.
2017-05-05 11:05:28 -07:00
Megan Wachs 325f17f6ec Merge pull request #43 from riscv/read-from-0
Read from 0
2017-05-05 09:30:24 -07:00
Megan Wachs 95a2eb157a riscv-013: more consistent parens 2017-05-01 09:42:11 -07:00
Megan Wachs 458bb20699 riscv-013: Correct sign extension of address on read_memory for lower bits as well 2017-05-01 09:39:59 -07:00
Megan Wachs 8462750357 riscv-013: Correct sign extension of address on read_memory 2017-05-01 09:37:48 -07:00
Megan Wachs ad1cf13ef4 Correct debugging print in read_memory 2017-05-01 08:35:10 -07:00
Palmer Dabbelt 16de5044d4 Fix an assertion when reading from 0 2017-05-01 08:33:01 -07:00
Palmer Dabbelt ba3a56937b Correct previous hart caching logic 2017-05-01 08:32:43 -07:00
Palmer Dabbelt 1ec607c726 Clean up unused read_memory code 2017-04-27 12:56:01 -07:00
Palmer Dabbelt 4116b97d6e Correct an off-by-one in argument parsing 2017-04-26 15:17:11 -07:00
Palmer Dabbelt 17d04aded3 Keep calling the old poll on v0.11 targets
This is another thing that should be fixed correctly.  Essentially this
just uses the old codepath, which works for v0.11.
2017-04-26 15:16:39 -07:00
Palmer Dabbelt 9d4df3420c Initialize all registers in examine
I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt.  This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.
2017-04-26 15:09:24 -07:00
Megan Wachs da66be0161 riscv: Fix some blocking compile warnings 2017-04-26 10:23:53 -07:00
Megan Wachs 1ab5d7b497 fespi: Allow the ctrl_base address specified as a parameter 2017-04-26 09:10:49 -07:00
Palmer Dabbelt 8dea2908b7 Add 64-bit and multihart support
This is a major rewrite of the RISC-V v0.13 OpenOCD port.  This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports.  This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around.  The changes are:

 * You can pass "-rtos riscv" to the target in OpenOCD's configuration
   file, which enables multi-hart mode.  This uses OpenOCD's RTOS
   support to control all the harts from the debug module using commands
   like "info threads" in GDB.  This support is still expermental.

 * There is support for RV64I, but due to OpenOCD limitations we only
   support 32-bit physical addresses.  I hope to remedy this by rebasing
   onto the latest OpenOCD release, which I've heard should fix this.

 * This matches the latest draft version of the RISC-V debug spec, as of
   April 26th.  This version fixes a number of spec bugs and should be
   close to the final debug spec.
2017-04-26 09:10:49 -07:00
Megan Wachs 3dc066382b Properly consider 'reset halt' and do halt or resume as needed 2017-04-10 12:03:15 -07:00
Megan Wachs 75e7c79b2a fespi: Reset may have occurred. Need to set TXWM again. There are probably more places that need this added. 2017-04-10 12:03:15 -07:00
Megan Wachs b04c6cb3ed riscv: Implement the assert/deassert reset functions for v13 2017-04-10 12:03:15 -07:00
Megan Wachs 7203102c25 Merge pull request #28 from sifive/readmem_autoexec
Readmem autoexec
2017-04-04 22:27:52 -07:00
Megan Wachs 14e26040b8 riscv: move value read to after autoexec is cleared. 2017-04-04 16:33:17 -07:00
Megan Wachs 9c1f6ea28b riscv: Correct the autoexec in read_mem 2017-04-04 16:22:55 -07:00
Palmer Dabbelt 69a8273da5 Merge pull request #23 from sifive/w1-to-clear-cmderr
riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.
2017-03-30 15:10:56 -07:00
Megan Wachs eb90a5e05e riscv: Use write-1-to-clear for CMDERR, not write 0 to clear. 2017-03-30 14:27:28 -07:00
Palmer Dabbelt 7df6804934 Revert "(WIP) Force algorithms to 64 bit"
This reverts commit 466b7b4881.
2017-03-23 19:46:54 -07:00
Palmer Dabbelt 466b7b4881 (WIP) Force algorithms to 64 bit 2017-03-23 19:21:02 -07:00
Palmer Dabbelt ae51b92480 some device 2017-03-23 14:51:30 -07:00
Palmer Dabbelt 03fa9d22c4 Don't set abstractauto at the start 2017-03-23 14:50:40 -07:00
Palmer Dabbelt 84fa7aa916 Merge pull request #21 from sifive/read_memory_retry
Read memory retry
2017-03-22 18:00:44 -07:00
Megan Wachs a7499161e0 Merge remote-tracking branch 'origin/riscv' into read_memory_retry 2017-03-22 17:53:23 -07:00
Megan Wachs c61b3efe9a riscv: Retry failed memory reads 2017-03-22 17:51:46 -07:00
Palmer Dabbelt 5f9cc2ce5f Turn off autoexec after read_memory() 2017-03-22 14:28:39 -07:00
Megan Wachs 98420e377a riscv: add missing variable declaration. 2017-03-21 23:47:21 -07:00
Palmer Dabbelt 09da0c812f Clear autoexec correctly 2017-03-21 17:20:11 -07:00
Palmer Dabbelt 6033850415 Wrong autoexec 2017-03-21 17:20:11 -07:00
Palmer Dabbelt 0c790d385d Builds 2017-03-21 17:20:11 -07:00
Megan Wachs c09ccbcc7c Merge pull request #20 from sifive/delay_after_autoexec
riscv-v13: wait for idle in read_memory
2017-03-21 13:18:26 -07:00
Megan Wachs a70e628620 riscv-v13: wait for idle in read_memory
read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.
2017-03-15 17:23:21 -07:00
Tim Newsome bb39d3b17e Remove more cruft.
Change-Id: I24d545cc259927301851fad446f812e95fd1c557
2017-02-27 20:27:07 -08:00
Tim Newsome 8785b256cb Merge pull request #18 from sifive/halt_correctly
riscv: Ensure that hart is halted before attempting to examine it.
2017-02-27 20:17:42 -08:00
Megan Wachs 7f13e90505 riscv: Ensure that hart is halted before attempting to examine it. 2017-02-27 18:53:50 -08:00
Tim Newsome b4d38d0997 Remove cruft.
Change-Id: I3a370aa3a478ab84c9b2afff7b3f581bd7dc5e06
2017-02-25 10:40:56 -08:00
Tim Newsome 6f1a498ab9 Use DCSR constants from the debug spec.
Replace the constants with the ones from the ISA spec, since those are
not updated as often.

Also delete a bunch of old code.

Change-Id: I9201b1455d64a9d2d203bb362fefaa68cbf35aeb
2017-02-25 10:34:46 -08:00
Tim Newsome 8f6ddc92e8 Update bits to latest spec.
Change-Id: Ib09e1da81c6c0e7c9c6b69e9fe31eda20e3cd6e0
2017-02-25 10:17:27 -08:00
Tim Newsome 3bd661b679 Speed things up by ignoring return values.
The remote bitbang implementation is really slow when reading back data.
During many operations, like writing a block of memory, we don't need to
see the return data. By communicating this to the lower layers, we get
huge speedups. Downloads to spike now are 295KB/s.

That means the gdbserver.py download test now runs to completion,
unfortunately it fails. Everything else is still passing, though, so I'm
committing this change.

Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
2017-02-22 16:04:36 -08:00
Tim Newsome f9168b09d0 Optimize memory write code, used in download.
To spike now we download at 5KB/s. But in real hardware performance
should be pretty OK now.

Change-Id: Ie6086cf156c9a00ac55400870346e27b28e3c755
2017-02-21 20:31:50 -08:00
Tim Newsome 4e8cf4aeb5 Better error checking in memory access.
Change-Id: I985afa433a09f833137f2e244b7eaad2630f6b1a
2017-02-20 17:53:18 -08:00
Tim Newsome aba0c0973d Properly restore s0 and s1 on resume.
Now 33/39 of the gdbserver tests pass!

Change-Id: I0cb38fbbcdc2c037ff0ec77229e79f24fa021663
2017-02-20 15:47:31 -08:00
Tim Newsome 3173314f28 Fix access FPU registers again.
Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.

Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
2017-02-17 19:03:32 -08:00