Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
Kinetis family employs strange concept of Flash Configuration Field at
address 0x400 of program flash. Writing incorrect data to FCF may
permanently lock the device.
The change introduces 'kinetis fcf_source protection' mode. In this mode
write of flash image data to FCF is prevented. FCF data build from
protection (set by 'flash protect' command) are written instead.
FCF data are written also just after erase of relevant sector. It
protects device from locking security by reset or power cycle after erase.
prot_blocks array is used as protection blocks have bigger size than sectors.
Alignment and padding programming sections is rewritten to fix
writing with not section boundary aligned begin.
Change-Id: I9fc8bd37d6f627fb8ed7abb7f7560e78a740b195
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3562
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Add kinetis_ftfx_decode_error() to show flash error type in human
readable message.
Add kinetis_ftfx_prepare() to prepare flash module just once in
command (not each time kinetis_ftfx_command() is called).
Change target_read/write_memory() to target_read/write_u8/32().
Make ftfx_fstat parameter of kinetis_ftfx_command() optional.
Longword flash write:
Fix huge memory leak after write of unaligned block.
Check flash address alignment properly.
Do not fill whole padding buffer but its end after original data.
Remove duplicite padding.
Change-Id: Ia5e312909f68d3cc724c8cbffe1cd903b9102124
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3561
Tested-by: jenkins
Reviewed-by: Steven Stallion <stallion@squareup.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Originally flash/nor infrastructure assumed protection blocks identical
to erase sectors. This assumption is not valid for many flash types.
Driver code fixed the problem either by increasing sector size to
size of protection block or by defining more protection block than
really existed in device. Both cases had drawbacks.
The change retains compatibility with the old driver.
Updated driver can set protection blocks table independent
of sector table.
Change-Id: I27f6d267528ad9ed9fe0a85f05436a8ec17603a4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3545
Tested-by: jenkins
Reviewed-by: Steven Stallion <stallion@squareup.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The change prevents starting mass_erase in unstable state of MCU
(RESET/WDOG loop).
mass_erase of secured MCU using manual reset button is supported.
Timeouts are measured by timeval_ms() instead of iteration count.
mass_erase timeout prolonged to 16 seconds because aborting
mass_erase in progress (deasserting reset) leaves the device
in security locked state.
Change-Id: I6605532df56080a54c2a1dfe49094e3db4ce534a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3551
Tested-by: jenkins
Reviewed-by: Steven Stallion <stallion@squareup.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Kinetis driver checks MDM STAT register to detect secured state of MCU.
Original version often reported a blank device as secured one.
Change #3010 has not fixed all false reports.
After changes in arm_adi_v5 infrastructure secured devices was not detected
at all.
New algorithm uses multiple MDM STAT reads and counts MDM_STAT_SYSSEC and
MDM_STAT_FREADY bits. Both secured MCU and MCU locked-up in RESET/WDOG loop
are detected reliably.
Detection is run in both kx.cfg and klx.cfg from examine-start event,
not examine-end as before. Event is configured only for non hla adapter.
Minor fix in klx.cfg: commented out adapter_khz 24000 in reset-init.
Such frequency is not supported in VLPR CPU mode and with JTAG.
Change-Id: I2ec2b68c45bde9898159cd15fbdcbcfa538c41d9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3547
Tested-by: jenkins
Reviewed-by: Steven Stallion <stallion@squareup.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
NXP (nee Freescale) documents the mass erase procedure using the MDM-AP
block in AN4835. Existing support for this feature did not properly
handle boards without SRST. This patch updates the mass_erase command
such that it works correctly on these boards. Additionally, the core is
left in a halted state once complete to prevent reset loops due to the
watchdog as reported by some users.
Since the MDM-AP provides an additional method of halting and resetting
the core that is disconnected from the DAP, additional commands are
provided to manage this state. These commands are particularly helpful
when connecting to a target with an unknown state.
Change-Id: I40f006d5d964befb12b019c5d509988decdd3f91
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/3540
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
at91sam7_read_part_info() walks throw all flash banks following
current one.
I don't know why it has to do it at all (possibly for multi-bank
devices like SAM7S512), but if there is more than one target in JTAG
chain, this lookup can touch flash bank of another (possibly not
halted) target, which cause probe error and current command
execution abort.
[andreas.fritiofson@gmail.com]: Change to for-loop and reduce
indentation
Change-Id: Ide50e93578786e1250f7a0fd0e3d296247924814
Signed-off-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2610
Tested-by: jenkins
This change adds JTAG transport in pass-through mode
to the cmsis-dap driver. The patch is originally from
Phillip Pearson <pp@myelin.co.nz>, with additions
by Maksym Hilliaka <oter@frozen-team.com>
Change-Id: I88d918d6576e9d875c3b611f29f255581e6a5424
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3568
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Although the documentation suggested this worked, and it is implemented
for tcl_port and telnet_port, the directive was not recognized for
gdb_port.
Change-Id: I38d95ee879ec3f6d551603b7313749a21e0e498e
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/3637
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
- added ids for various parts
- rewrite of sector allocation to deal with dual-bank F76x/77x
- single- / dual-bank mode for F76x/77x
- sector protection adapted for F76x/77x in dual-bank mode
- handling of additional option bits (28-31) in FLASH_OPTCR
in options_read and options_write for F42x/43x/469/479/7xx,
options bits 0-1 masked out
- check for sensible value of user_options in options_write
- some #defines clarified, non-needed ones removed
- docs updated (options read, options write)
Change-Id: Ie4db80e60baa7d2663e024ab1f278640b1ce901b
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/3526
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This patch removes the display_str member in the thread_detail struct.
This member was not being used and provides no additional benefit over
the thread_name_str and extra_info_str members. This change is made in
preparation of support for the qXfer:threads:read packet, which will
modernize how thread information is shared with GDB.
Change-Id: I1f8bc6325e6aa790e02ea6caee9d6f44c5fedf36
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/3558
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Only report non-erased or unknown sectors or if bank is fully erased.
Change-Id: I94f0bc2a0d6529d1ea5f66b284cefd6a2c61fe39
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3501
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
1) wrong last bit was shifted out in the end of IRSHIFT/DRSHIFT in
jlink_execute_scan()
2) TDI buffer was not cleared in jlink_tap_init(), results in wrong
data shifted out to the TDI and "Bad value '00000000' captured
during DR or IR scan" error message.
3) sizeof(tdi_buffer) was used in memset() to clean tms buffer. It
is the same as sizeof(tms_buffer), but shoud be fixed to make source
code consistent
Change-Id: I13f26d1c3e88eefc3856fe2b8542fb0ccea6acb1
Signed-off-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Reviewed-on: http://openocd.zylin.com/3394
Tested-by: jenkins
Reviewed-by: Harry Zhurov <harry.zhurov@gmail.com>
Reviewed-by: Anton Gusev
Reviewed-by: Михаил Цивинский <mtsivinsky@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Corrected 2 Silicon IDs that were swapped.
I've tested with a CY8C4125AXI-483 and confirmed
that the device is recognized correctly now.
Change-Id: I6fcbee33558d8feec9abf6052df3f15523379c48
Signed-off-by: George Ioakimedes <georgeioak@gmail.com>
Reviewed-on: http://openocd.zylin.com/3619
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
target_run_flash_async_algorithm() ignored abort from target
(rp set to 0) when raised after all data have been written in fifo.
I could result e.g. in not reported error during flash write.
The change adds rp test after target algorithm has finished.
Change-Id: Iadd93371e4a4602737be10079479285d81ae41b2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3560
Tested-by: jenkins
Reviewed-by: Steven Stallion <stallion@squareup.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Using the presence of the 'chSysInit' symbol for detection of
ChibiOS is dangerous because this symbol may not be available
if link-time optimisation is used.
This patch removes this reliance, so the symbols 'ch' and 'ch_debug'
are the only things required for ChibiOS detection.
If 'ch' is present but 'ch_debug' is not, an info message suggests
that Chibios might be present without its registry being enabled.
This message has been reworded a little to make it slightly more
equivocal because the chances of a false positive message are
increased.
Addresses bug #121, "ChibiOS rtos detection fails with LTO enabled".
Change-Id: I5ef224735c06446751adee010ce75be4f30f0403
Signed-off-by: Andy Pomfret <cooperised@gmail.com>
Reviewed-on: http://openocd.zylin.com/3381
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
- FPU detection and FPU register support added for Cortex-M7.
There is no apparent difference between FPv4 and FPv5_SP but ...
- Autoincrement range for MEM-AP added for Cortex-M7
This patch together with #3526 replaces #3123 except for stm32f7x.cfg.
Change-Id: I5ed5392e3835674160563ff37d67622a7bf2c877
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/3531
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
If WAIT recovery fails (times out), an ABORT command is issued to the
DAP but under some conditions the SSTICKYORUN bit in CTRL/STAT is not
cleared as well, which renders the DP unusable. This happens when
trying to access e.g. the ROM table of powered-down cores, on many
targets.
Change-Id: Id0a7ba6180069eee562871314f520f938df9718f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3476
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Allow using physical addresses with mem2array and array2mem. In order
to minimize the impact on existing scripts, "phys" is added as an
optional 5th parameter to both commands.
This patch also adds "phys" variants to the memwrite/memread commands
in memory.tcl.
Change-Id: Ia6307f9d861789e7f3ccf1f98961d666bf8d85d6
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3387
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Sometimes it is necessary to resume into a different state (ARM/Thumb)
than at debug state entry. According to the documentation this should
be possible with "arm core_state arm|thumb" before the resume command,
however the original code also restores the original CPSR, which
overrides whatever state the core was set to. This seems to work on some
cores (e.g. Cortex-A5) but not on others (e.g. Cortex-A9). Using the "BX"
instruction to set resume PC and core state works on Cortex-A9 and
ARM11, but is not sufficient on Cortex-A5, where an explicit write to
the PC (MOV pc, r0) is required additionally.
Change-Id: Ic03153b4b250fbb8cf6c75f8e329fb34829aa35f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3386
Tested-by: jenkins
Reviewed-by: Alexander Stein <alexanders83@web.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
1986VE1T and 1986VE3T have issue with flash acceleration engine described
in their errata (issue 0007).
After programming flash acceleration engine's buffer contains old data,
and therefore first read data are wrong. Because of this verification after
programming fails always. Recommended workaround for the issue is to flush
flash accelerator's buffer. To do so it's necessary to read at least 64
bytes of flash through accelerator.
Reading bytes through JTAG using default_flash_read doesn't help.
It seems that reading should be done by uC itself.
Change-Id: I18ef464a68ad5c5b16d3933f31ca61f8e2e7cca3
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-on: http://openocd.zylin.com/3509
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
First, fix the timeval_ms() implementation to not have K&R but ANSI
argument semantics by adding a missing void.
timeval_ms() returns an int64_t, not uint64_t or long long. Consistently
use int64_t for variables and PRI*64 as format string.
While at it, change a few related variables to bool for clarity.
Note that timeval_ms() may return a negative error code, but not a
single caller checks for that.
Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3499
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
A developer tool: Direct access to AP registers can be useful
for handling vendor specific AP like Freescale Kinetis MDM or Atmel SMAP.
Change-Id: Ie2c7160fc6b2e398513eb23e1e52cbb52b88d9bd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2777
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Some installations of OpenOCD are used in restricted environments that
do not permit binding to public interfaces.
This patch does not affect the default behavior to listen on all
interfaces, however it does give the option to restrict services by way
of the bindto command.
Change-Id: Id51bd64b376a8c62dd47b08b4d834872925e6af2
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/3534
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Today the reset option for connect_assert_srst is not done for SWD.
This patch adds this to SWD and make it possible to connect to targets which might disable JTAG interface when running.
Change-Id: Ib89f7cf59b628e8f0b5fca9dd9e362e383c4b99f
Signed-off-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-on: http://openocd.zylin.com/3018
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds the 'data_swap' parameter to the CFI driver, which enables
swapping of data bytes when writing/programming words to the flash.
Note, that this specifically means that bytes are not swapped when
writing command words to the flash chip. Unless you are using the SAP
in an LS102x chip to program an attached 16-bit NOR flash, you hopefully
do not need this!
Change-Id: I1e6f7169da36f373c880d1756d9c21c9957acc50
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Reviewed-on: http://openocd.zylin.com/3109
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The SAP in LS102x SoC's from Freescale is able to read and write to all
physical memory locations, independently of CPU cores and DAP.
This implementation is 100% based on reverse-engineering of JTAG
communication with an LS1021A SAP using a JTAG debugger with SAP support.
And as such, this code is for now "works-for-me", pending verification
by other OpenOCD users, or even better, actual information from Freescale
on the SAP interface.
Change-Id: Ibb30945e017894da5c402f9f633fc513bed4e68c
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Reviewed-on: http://openocd.zylin.com/3096
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Also make GPL notices consistent according to:
https://www.gnu.org/licenses/gpl-howto.html
Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3488
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add rules to build armv4_5_crc.inc, and convert the code to target
endianness the least intrusive way.
Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3473
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Add rules to build armv4_5_erase_check.inc, and convert the code to
target endianness the least intrusive way.
Drop an unused word from the assembler sources to make the ARM bytecode
fully match that of armv4_5.c and to not break ARMv4 assumptions.
This completes the build rules for contrib/loaders/erase_check directory.
Change-Id: I36be7a944e26142088195fa3fb072d4e577bf328
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3135
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add rules to build armv7m_crc.inc and include it via preprocessor.
Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3474
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Clean up the working area in case writing fails.
Change the error handling paradigm to avoid duplication.
Change-Id: Ie3f95f992a98a1325428e4032a1c17346d4c9977
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3472
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Clean up the working area in case writing fails.
Change the error handling paradigm to avoid duplication.
Change-Id: I95bb12fbe7c80b594e178468bcd4f6387c682c93
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3471
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andreas Fritiofson says "If any adapter driver does not work with
arbitrary lengths of individual fields, it's a bug."
https://sourceforge.net/p/openocd/mailman/message/35091945/
Note also that lengths of at least 96 bits are already in use, eg. in
mips_ejtag_add_scan_96().
Change-Id: I62a150adc75c0ef78827683ca8d0a8e90310a982
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/3491
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
When using SWD rather than JTAG transport, the lpcspifi driver complains:
Error: Device ID 0x0 is not known as SPIFI capable
Error: auto_probe failed
This is because target's JTAG tap->idcode is zero for SWD.
Drop this check completely and hardcode the addresses for now. Neither
the JTAG TAPID nor the SWD IDCODE are unique enough to detect the exact
chip model and thereby its memory map.
Change-Id: Ic230e3e989a3e1f1a5b3bae68bdb34e5ef55d392
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3089
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn
or CortexXn. Further it's Cortex-M0+, not M0plus.
Cf. http://www.arm.com/products/processors/index.php
Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.
Found via:
git grep -i "Cortex "
git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu"
git grep -i "CortexM"
Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3483
Tested-by: jenkins
Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Change type of use_raw to boolean. This parameter was already
assigned a boolean variable (in COMMAND_PARSE_ENABLE) and used
as a boolean.
Change-Id: I22f8308246cb25ec9ec2395599e406160410a2a8
Signed-off-by: Ivo Manca <pinkel@gmail.com>
Reviewed-on: http://openocd.zylin.com/3496
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Return ERROR_NAND_DEVICE_NOT_PROBED to prevent calling functions
from segfaulting when nand device has not yet been probed (ie nand
verify)
Change-Id: Ibc4da0aad00e6cc6c83008882b054d981453dc36
Signed-off-by: Ivo Manca <pinkel@gmail.com>
Reviewed-on: http://openocd.zylin.com/3495
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Memory accesses are not made through the APB-AP, they are made through
the CPU (which happens to be controlled over the APB-AP). Rename all
irrelevant uses of the APB-AP term. And fix the long standing typo in
the function names...
Change-Id: Ide466fb2728930968bdba698f0dd9012cc9dbdf9
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3216
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
According to the MSP432P4xx Family TRM (SLAU356A) Figure 4-7,
0x9AF is the part number for MSP432P401xx devices.
Verified on TI MSP-EXP432P401R LaunchPad.
Change-Id: I22b57c42f2a0dc8263fab6b480cf8c169c7dc295
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3486
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This was found on multiple XMC4500:
Valid ROM table present
Component base address 0xe00ff000
Peripheral ID 0x00001c11db
Designer is 0x0c1, Infineon (Siemens)
Part is 0x1db, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
On multiple XMC4700 and an XMC4800 this was found instead:
Valid ROM table present
Component base address 0xe00ff000
Peripheral ID 0x00001c11df
Designer is 0x0c1, Infineon (Siemens)
Part is 0x1df, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
Name them "XMC4500 ROM" and "XMC4700/4800 ROM" respectively.
Change-Id: If369a6d16524004ba439b878f090a313a9f3a760
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3482
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Not documented in the Reference Manuals but found on multiple XMC1100/1202:
Valid ROM table present
Component base address 0xf0000000
Peripheral ID 0x00001c11ed
Designer is 0x0c1, Infineon (Siemens)
Part is 0x1ed, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
Name it "XMC1000 ROM", since it didn't differ between XMC1100 and XMC1200.
Change-Id: I98a5a524c0d0836f395400fbac24fd496b2ec141
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3481
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
ulink_calculate_frequency() is used exclusively when
_DEBUG_JTAG_IO_ is set, no need to compile this
function if it is not used.
Declaring it static in the same commit.
Change-Id: I243ffdf69a1dc3bee6d16e4bb8d78396b6ea5144
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3241
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Consistently increase the space-indentation of the .full values to
nicely align with the new "Qualcomm QDSS Component v1" .type value.
Change-Id: Icd28d8f3fc7c3afcccb9dcfe138ac57d64927d1a
Suggested-by: Freddie Chopin <freddie.chopin@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3480
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
Note:
WCR (Wire Control Register) is replaced by DLCR (Data Link Control
Register). And only TURNROUND field is modifiable.
[andreas.fritiofson@gmail.com]:
Rename DP_IDCODE to DP_DPIDR as well.
Sort list by address and align it using spaces instead of tabs. Add
comments about supporting DP versions.
Remove non-functional wcr command completely.
Change-Id: Ic6b781b07c8eead8b0237d497846d0da060cb1ba
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3244
Tested-by: jenkins
Instead of placing Atmel last, after ANY_ID, place it after ARM (it's
arm_adi_v5 despite 0x4BB) and sort it with the other vendors, i.e.
before ADI and Qualcomm. Adapt column alignment.
Drop the redundant "Atmel" comment to clarify that Analog is not Atmel.
Change-Id: Ic06785db079cf58d49815a639236636c180e5e17
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3479
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
On APQ8016 was found a CoreSight component designed by
Qualcomm, according to db410c HRM [1] it has a partnumber
following this schema:
[11:8] is 0x4 meaning Qualcomm designed Coresight component in QDSS. Reads as 0x4.
[7:6] is Subsystem/core family ID (e.g. denote QDSS family or generation).
[5:4] is Subsystem/core configuration options (e.g. denote cache options, etc.).
[3:2] is Subsystem/core fuse options.
[1:0] is Subsystem/core future use field
Reads as 0x440.
[1] - https://developer.qualcomm.com/download/sd410/hardware-register-description-qualcomm-snapdragon-410.pdf
Change-Id: I9b4b41fd17c59d2f5ae35b53278d06d6087665f8
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3408
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
On hi6220 'dap info' returned some unknown components from ARM.
Collected from ARM docs, mostly ROM table entries.
Typo fix for Cortex-M3 FPB.
Change-Id: I96bbf7349061937b3afc8bb8d6d1650f2609f82d
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3407
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Initial release of Ambiq Micro Apollo flash driver
supporting our sub-threshold (low power) Cortex M4F part,
and Evaluation Kit.
We have been shipping openocd to our customers for about one year.
The EVK boards are SWD only using ftdi. We also use two of the
other COM instances to display debug information.
It takes about 15 seconds to flash 512K, and mass erase is
about 5 seconds.
Tested by internal verification group, FAE's, and customer sites.
Merged commit 'refs/changes/17/3417/1' as suggested. Makefile.am
and drivers.c follow the new format to avoid conflicts.
Removed unused fault_capture command.
Added documentation for flash driver.
Change-Id: Iae92d869369c6827244f0071f9cb522d8d91fed8
Signed-off-by: Rick Foos <rfoos@solengtech.com>
Reviewed-on: http://openocd.zylin.com/3230
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Clean up working area in case writing fails. Probably inherited from
armv7m_blank_check_memory(). Fix adapted from armv7m_checksum_memory().
Change-Id: I784bef481d1eba833ab6a9c34249fe9d43a16081
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3470
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Clean up the working area in case writing fails.
Adapted from armv7m_checksum_memory().
Change-Id: I4e5950f568ed70a72a1dcfd77e3321110b17e1de
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3469
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Spotted by gcc:
arm7_9_common.c: In function ‘arm7_9_unset_breakpoint’:
arm7_9_common.c:353:4: error: this ‘if’ clause does not guard... [-Werror=misleading-indentation]
if (current_instr == arm7_9->thumb_bkpt)
^~
arm7_9_common.c:356:5: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘if’
if (retval != ERROR_OK)
^~
The logic won't change once the braces have been added, as the new 'retval'
check only makes sense within the if().
Change-Id: I6a303e118f2150e5eb25c9268ad06de5d8a533b2
Signed-off-by: Aleksander Morgado <aleksander@aleksander.es>
Reviewed-on: http://openocd.zylin.com/3477
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Among other things, this fixes building on Cygwin and MSYS.
Change-Id: I8bdceb49dc72b5f666388cfd97876eba8e1d2b13
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3478
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The ioutil helper functions copyfile and copydir were last and only used
in ecosboard.c which has been removed with commit 39650e22.
Removing the dead code.
Change-Id: I36c7c4c5009d755b4513a14a9f9e214d1ee500e8
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3240
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The cortex_a specific assert_reset function must only apply nSRST if
the reset configuration states that JTAG can be used while nSRST is
asserted.
Change-Id: If604a65fdea5bcb46ec723ada547a4e8d6fa8c59
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3356
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
For STLINK_SWD_AP_FAULT git://git.ac6.fr/openocd commit 657e3e885b9ee10
returns ERROR_OK with the comment:
Change in error status when reading outside RAM.
This fix allows CDT plugin to visualize memory.
Change-Id: Id8e220961b748ef9467fd84de62b1dc84ace63f8
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3373
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The capability to lock the debug interface on EFM32
controllers was lacking in OpenOCD.
After receiving some pointers by zapb_ and PaulFertser
on IRC (thanks guys!) I have added this capability.
This works by writing the required bits in the debug
lock word to '0'.
Note: there is currently no way to re-enable the debug
interface from OpenOCD as doing this requires specific
pin wiggling that is currently not implemented yet.
However: having the capability to lock the debug interface
is useful when building a volume programming jig.
You can flash the program code, verify and then
lock the debug interface so that the device cannot
be read when it is deployed in the field.
Change-Id: If2d562dfdb4b95519785a4395f755d9ae3d0cf12
Signed-off-by: Lieven Hollevoet <hollie@lika.be>
Reviewed-on: http://openocd.zylin.com/3389
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
If an error occurs during xmc4xxx_blank_check_memory() aka .erase_check,
it would break out of the loop over flash sectors and return ERROR_OK.
Instead return the error code so that tcl.c can notify the user.
Change-Id: Ie2c1b7933eef2b240b28f8a292634fbbf5b31706
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3425
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The function libusb_get_port_numbers(), required for the command
ftdi_location, is only available in recent version of libusb1.
Compilation will break if the function is not available. This patch
enables the command only if libusb1 contains the necessary function.
Change-Id: I091e72dafa4ed22eea51692751d43246a8152987
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3396
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The parts are listed in Rev I of the Datasheet
Change-Id: Icdd9108a0f1f19f666fce79de7f25df9f46de866
Signed-off-by: Peter D. Gray <peter@conalgo.com>
Reviewed-on: http://openocd.zylin.com/3424
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
I suppose 0xff300008 is the correct value for EJTAG_V20_DBS.
20 miliseconds is too much for scan delay, 2ms is enough in mips_m4k scan_delay handler.
mips32 scan_delay has the correct value.
Change-Id: Ie9dc650065a58e845687058a4c930f85909beec9
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/2271
Tested-by: jenkins
Reviewed-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
BMIPS always needs 2 additional instructions to reach the core.
Seems there is a 2 instructions fifo between the tap and the core, or it behaves in this way.
No idea of the purpose of this fifo, I can only guess.
Of course function mips32_pracc_clean_text_jump() must add this additional instructions (NOPs).
Only tested on bcm3348..
Change-Id: I3183d3ce865d469d7262ba4b15446e5743a5f1df
Signed-off-by: Salvador Arroyo <salvador@telecable.es>
Reviewed-on: http://openocd.zylin.com/2270
Tested-by: jenkins
Reviewed-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The XMC1000 family uses a very different flash interface from XMC4000.
Tested on XMC 2Go and XMC1100 Boot Kit.
Change-Id: I3edaed420ef1c0fb89fdf221022c8b04163d41b3
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3418
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
Part IDs taken from
Atmel-42402C-SAM L22_Datasheet_Complete-01/2016
(revision C)
Change-Id: I1eb76a92097a8327da10faa0551e7fc962a549f8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3426
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Before this change jim_target_reset() checked examined state of a target
and failed without calling .assert_reset in particular target layer
(and without comprehensible warning to user).
Cortex-M target (which refuses access to DP under active SRST):
If connection is lost then reset process fails before asserting SRST
and connection with MCU is not restored.
This resulted in:
1) A lot of Cortex-M MCUs required use of reset button or cycling power
after firmware blocked SWD access somehow (sleep, misconfigured clock etc).
If firmware blocks SWD access early during initialization, a MCU could
become completely inaccessible by SWD.
2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive
to SWD, reset command does not work even if it could help to restore communication.
Hopefully this scenario is not possible under full JTAG.
jim_target_reset() in target.c now does not check examined state
and delegates this task to a particular target. All targets have been checked
and xx_assert_reset() (or xx_deassert_reset()) procedures were changed
to check examined state if needed. Targets except arm11, cortex_a and cortex_m
just fail if target is not examined although it may be possible to use
at least hw reset. Left as TODO for developers familiar with these targets.
cortex_m_assert_reset(): memory access errors are stored
instead of immediate returning them to a higher level.
Errors from less important reads/writes are ignored.
Requested reset always leads to a configured action.
arm11_assert_reset() just asserts hw reset in case of not examined target.
cortex_a_assert_reset() works as usual in case of not examined target.
Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2606
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Cortex-M0+ and M4 motor control MCUs KV10, KV11, KV30, KV31,
KV42, KV44 and KV46 added to SDID identification.
Watchdog disable code changed to work on Cortex-M0+ (KV1x)
Protection size set to 1K for 16K flash devices (KV10Z16)
- cherry picked from Andrey Smirnov's change #2051
Change-Id: Ia6f4868eaf7e2cb6ad6a736210c703a67e0027be
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3235
Tested-by: jenkins
Reviewed-by: Kyle Manna <kyle.manna@fuel7.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Change-Id: I55ab830aed34a02c53f3419facc81c7354368e30
Signed-off-by: Peter D. Gray <peter@conalgo.com>
Reviewed-on: http://openocd.zylin.com/3422
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Färber <afaerber@suse.de>
To avoid conflicts between flash drivers being added, consistently use
an alphabetical sort order for the three places new drivers get added:
* Makefile.am NOR_DRIVERS (note: automake disallows a trailing backslash)
* drivers.c struct flash_driver forward declarations
* drivers.c flash_drivers array
Change-Id: Idcd6a8e12821ef10958a6b3ad7bac0dc63cadd08
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3417
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Taken from git://git.ac6.fr/openocd commit e8ed67c42227b7072
STM32F446 (0x434) now is's own case.
Change-Id: I5061db7102b4c923c9f39d3d2f0cc69d29fca0a4
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3375
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Old code waited only for 7 bytes and didn't handle buffer wrap-around, but
was functional despite.
Change-Id: Iceaf7be1e51368b2ec0a8722cc9ac16d12f9aa63
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3140
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add new structure for for working with FPU thread in thread view.
This modification support both stacking.
When FPU is activated, LR must be validated to check if the FPU
register are push on the stack. This is mandatory to find the correct
stack pointer position.
the modified code was inspired and adapted from
88d2003bb8
Change-Id: I6641926aa14e7216cacb399cbc8bb0db324cc9fc
Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-on: http://openocd.zylin.com/3397
Tested-by: jenkins
Reviewed-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Reviewed-by: Harry Zhurov <harry.zhurov@gmail.com>
Reviewed-by: Anton Gusev
Reviewed-by: Михаил Цивинский <mtsivinsky@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested with MKE04Z8VTG4, MKE02Z64VLC4 and MKE02Z64VLD2.
Change-Id: I606e32a2746a3b96d3e50f3656ba78d40c41c1ea
Signed-off-by: Ivan Meleca <ivan@artekit.eu>
Reviewed-on: http://openocd.zylin.com/3380
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
There is no reason why not probe running target.
Initial gdb connect to running target is now possible without
halt in gdb-attach event.
Change-Id: Iacc4a231587d378168b18db871582f1086504831
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3382
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This feature is required for boards that use a programmatical way
to reset the cpu, like the TI Pandaboard with OMAP4. The board only
has a 14 pin JTAG header that doesn't feature SRST and is reset by
direct write to the PRM_RSTCTL register.
iMX6 can be reset through triggering the on-chip watchdog, but for these
methods to work reliably, access through the AHB-AP without interaction
with the CPU core is necessary.
Change-Id: I9a07a536adda83cc2f93e504384c8c7f0306220b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3359
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch adds a 'ftdi_location' command to select an adapter by usb
bus number and port path.
This is helpful if you have a rack full of adapters in a testing or
manufacturing setup where the only constant is the physical usb bus
location of the adapter you want to address. Vid:Pid are not unique,
serial number _may_ be unique (and maybe not with embedded adapters) but
will change when a new target is plugged.
Specifying a location allows to understand instantly which board failed
bringup or testing.
Change-Id: I403c7c6c8e34fe42041b3f967db80f3160a4f1a3
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3351
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add support for S6E2DH MainFlash. VFlash is not implemented.
Briefly tested with SK-FM4-176L-S6E2DH V110 board.
Change-Id: If7c523d8c75307bc1494bbf4cca3eed0272e8e01
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3158
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
These appear to be just additional flash size configurations.
Entirely based on manual, untested.
Change-Id: I4460dc1a588335df8fc0a385d24513a4e35b6951
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3157
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On the ARM PB1176JZF-S the system comes up in secure monitor
mode after reset. However the modebits in CPSR form the value
28 (0x1c) and CPSR is 0x800001dc deeming it UNRECOGNIZED.
Define this mode to be synonymous to mode 22 (MON) and things
start to work like a charm.
Change-Id: I001f7773ee1076202c0c633e466d2d833f7a1413
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-on: http://openocd.zylin.com/3196
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This adds necessary code to obtain data from the Info region which is
not memory-mapped so can't be read the usual way.
With this "flash read_bank" and "flash verify_bank" commands should
start to work as expected for the Info memory block.
Change-Id: I57e4b80fff577500cfa85954b625fe9c9ff92aa5
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3227
Tested-by: jenkins
Reviewed-by: Eldar Khayrullin <eldar.khayrullin@mail.ru>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Instead of documenting the file path as a comment and inline-commenting
the THUMB bytecode, include the hex array via preprocessor.
This assures the path is actually up-to-date and facilitates updating
the code.
Change-Id: Ieb0a7cd0bc14882ac96750f524616d9768a0c6f5
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3134
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Instead of pointing to the assembler sources in a comment and
inline-commenting the THUMB bytecode, place the hex array alongside the
assembler sources and include it via preprocessor.
Originally inspired by a typo in the file path during driver development,
but it also facilitates making changes to the assembler sources.
A Makefile is provided to help automate updating the bytecode. It is not
integrated with the automake system to avoid forcing an ARM cross-compiler
onto every user, i.e. after modifying the sources they need to be rebuilt
in that directory before building the usual way. ARM_CROSS_COMPILE= can
be passed on the make command line to deal with native ARM toolchains
or with varying prefixes of cross-toolchains.
Change-Id: I00ceb980a68c8554a180dd13719ac77b677a8bcd
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3133
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The Spansion FM4 family of microcontrollers does not offer a way to
identify the chip model nor the flash size, except for Dual Flash vs.
regular layout. Therefore the family is passed as argument and
wildcard-matched - MB9BFx6x and S6E2CC families are supported.
Iterations showed that ...
1) Just doing the flash command sequence from SRAM loader code for each
half-word took 20 minutes for an 8 KB block.
2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
3) Significant performance gains were achieved by looping in loader code
rather than in OpenOCD and by maximizing the batch size across sectors,
getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
(Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
gcc, objcopy -Obinary and bin2char.sh are used for automating the
integration of hand-written assembler snippets.
Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2190
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Flash driver for at91sam4 cpu's has been enhanced to recognise and support the SAM4N family.
Change-Id: I50c471a6053b52edffd8efdd8abfe516cc5c55ee
Signed-off-by: Colin Helliwell <colin.helliwell@ln-systems.com>
Reviewed-on: http://openocd.zylin.com/3242
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Error found by static code analysis using the semantic pattern
null_ref2/mini_null_ref2.cocci, see coccinellery.org
Change-Id: Ic817c29f0ccf2b41fc8f7d9a480ad30d6e5b7ab8
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3364
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A copy-and-paste error in the arm_disassembler opcode evaluation
disabled the recognition of MRRC instructions.
According to the arm architecture ref. manual issue E or later, MRRC and MCRR
instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5.
Error found by static code analysis using a semantic pattern to
detect duplicated tests xand.cocci, see coccinellery.org
Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3363
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The flash info command on stellaris platformes
"TI/LMI Stellaris information ... rcc is ..., rcc2 is ..."
presented the actual RCC2 register as rcc and an uninitialized variable
as rcc2 due to a copy and paste error.
Found using the semantic pattern da/da.cocci, see coccinellery.org
Change-Id: I6f920fc3e07fdc085ea8e2248fbc9453eb8393dc
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3368
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A struct member has been initialized twice. Found using the semantic
pattern da/da.cocci, see coccinellery.org
Change-Id: I0320afd60f1ba505758cc5bc0adcf27f572492fb
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3369
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Obsolete C source code semicolons were removed using the semantic patch
semicolon/semicolon.cocci, see coccinellery.org
Change-Id: I153b4995a9e028ebaf5f58c947821dc78345a777
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3367
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Writing to Intel CFI flash with unaligned tail bytes raised a false
error message although all data was programmed successfully. e.g.:
> flash write_image image 0x602e0000 bin
> Programming at 0x602e0000, count 0x00000002 bytes remaining
> couldn't write word at base 0x60000000, address 0x602e0000
> error writing to flash at address 0x60000000 at offset 0x002e0000
Root cause for this false error was a mixup of two result variables
introduced with ecc8041c.
Change-Id: Ib6b85293dbed946a36a307e5b198c47b901145bf
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3233
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is a nRF51822 variant, not a nRF51422 variant.
Change-Id: Ia199e0afa39408d7391a9655bad47eba2fd85f14
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/3105
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Simplify by printing one component per call, instead of one complete ROM
Table per call. Print common information the same way for all components,
including ROM tables, because ROM tables (at least the top level) contain
useful information in their identification registers, such as the
manufacturer of the SoC.
Print component designer name using the JEP106 helper when available.
Change-Id: Ic51bccd98acfae6886243500153fbdd567be2fae
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3182
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: James Mastros <james@mastros.biz>
Tested with EES-AA revision chips on Relax Kit for 5V Shields and
Relax Lite Kit.
Change-Id: I17d4479657bad0516d4c10c2ad7e745d59e678b7
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3136
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The cache is forced to zero to match the value expected by the DPIDR read
so the connect sequence is not destroyed by a SELECT update.
However, DPIDR and in fact all registers except address 4 are independent
of the current DPBANKSEL value. Change swd_queue_dp_bankselect() to use
this fact and avoid touching SELECT for those registers.
Change-Id: I0cd11925fb6adef481bbf45cc24ea2c6dab4b6fb
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3231
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Investigation:
- mem_ap_read_buf_u32() no longer exists.
- JTAG_DP_DPACC & JTAG_DP_APACC are defined in adi_v5_jtag.c now.
Change-Id: I136fc3f389a5a4eb9b68bc759ce653b6da7fa75e
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/3243
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
FTFx flash controller requires MCU in normal RUN mode.
Flash cannot be erased, programmed or blank checked in VLPR or HSRUN
modes.
VLPR mode is switched to RUN mode as it does not require any changes
in clock generator setting. VLPR can be active from reset on some
KLx devices (with some FOPT setting) so 'reset init' might not be
sufficient to get device to normal RUN.
Any other mode than RUN or VLPR is reported as an error.
Change-Id: I60f494ce0d534b04870c6219d9b05f66f7244433
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3012
Tested-by: jenkins
Command for partitioning FlexNVM to data flash and EEPROM blocks
Change-Id: Ia0ea65d72b0e5f23da330520284b0bd26435e444
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2991
Tested-by: jenkins
FlexRAM should be requested before any section programming.
Test FCNFG RAMRDY bit before issuing FTFx_CMD_SETFLEXRAM
to speed up operation and to cover pflash only devices.
Change-Id: Ib0f2d8e8ab8b1507cbf2b7f8565178ab79941f5d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2990
Tested-by: jenkins
kinetis_ftfx_command() did not use other struct flash_bank* members
than base->target. Switching first parameter to struct target*
enables use of kinetis_ftfx_command() without unnecessary bank
getting and probing.
Removed kinetis_securing_test: kind of dead code, same function
as command flash erase_address pad 0x400 0x10
Removed "NAND" word from help as flash is obviously NOR
Change-Id: I3f5fc295ef2bf42f3e913549949f2a36377f6367
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2988
Tested-by: jenkins
FlexNVM (data flash) is memory mapped at 0x10000000.
Driver used to send the same address to FTFx controller for erase/write ops.
This was wrong as FTFx accepts only low 24 bits of address.
To fix addressing for flash controller kinfo->prog_base was introduced.
Added FlexNVM protection check, blank check and data flash size calculation.
Blank check cannot use block operation on FlexNVM when EEPROM backup is enabled.
Removed non functional reassign logic and bank_ordinal stuff.
Now one can re-probe FlexNVM banks after nvm_partition change.
Change-Id: Ia60b938266963e5d056701278cdf7bf2f62a429a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2987
Tested-by: jenkins
This patch also addresses a problem with devices where no serial
number is available. For further details, see:
http://repo.or.cz/libjaylink.git/commit/7e0508d8487f65f71411117dff2e0b093e00bc80
Such devices are now ignored if device selection via serial number is
used.
Nevertheless, these devices are still usable by using the USB address
for device selection or just by omitting device selection. The latter
one is only possible if only one device is connected.
Change-Id: I5763db25e97ba3d924cb642da7e64e951e09ecb7
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3225
Tested-by: jenkins
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Check CMSIS-DAP adapter has serialnumber before pass it to wcscmp.
Keep looking for onother adapter if choosed one doesn't have correct
serialnumber.
Change-Id: I7d386a03cb49b9baf22073ae1c6b14269ed3b618
Signed-off-by: Andrii Anpilogov <anpilog@gmail.com>
Reviewed-on: http://openocd.zylin.com/3226
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is for targets where flash controller has reverse endianness
compared to target. For these, the 'bus_swap' parameter can be given to the
CFI driver, which will cause command CFI commands to be written with
bytes swapped. This is only for x16 CFI flash.
Change-Id: I698b768e92e65d160232e90b0e81a824e3c81a46
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Reviewed-on: http://openocd.zylin.com/3041
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Due to signal propagation delays, sampling TDO on rising TCK can become
quite peculiar at fast TCK rates. However, FTDI chips offer a possiblity
to sample TDO on falling edge. With this change, stable operation can be
achieved at 30MHz clock even over 10cm ribbon cable.
Change-Id: Icaf240535dae15512e3c60a944e22a5fbc1b0b06
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3180
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add support for the Intel Quark mcu D2000 using the new quark_d2xx
target.
Changes to the lakemont part are needed for the D2000 core and
backwards compatible with the X1000 one.
Change-Id: I6e1ef5a5d116344942f08e413965abd3945235fa
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3199
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
duration_elapsed and duration_kbps will not modify the struct duration
passed as function argument, hence it should be declared const.
Change-Id: I459c396952c78e907257e2c2f2c630abde92aaa8
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3232
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Commit 830d0c55c0 introduced
a regression in error recovery after reconnect:
If first SWD queue run in dap_dp_init() fails, DP_SELECT
does not get reset.
Change-Id: I947e2afe9933e4645a6141ece7816af8e6082cf2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3194
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Commit fd43be0726 introduced a
regression: since the register names were changed from those
traditional for MIPS to common GDB scheme the code that makes use of
them needs to be changed accordingly.
This commit restores pic32mx flash driver functionality.
Change-Id: Id18c739390fae36737a02dc30c363d0444f53b96
Reported-by: Louis Rannou <louson@users.sf.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3206
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
niietcm4_write() buffer padding:
add correct buffer padding for 16 bytes.
Args check in FLASH_BANK_COMMAND_HANDLER():
first version of the driver had 7 args, current - 6. This patch will fix
error when flash is rejected (current k1921vk01t.cfg has flash bank init
with 6 args).
Timeouts in flash flag checking procedure:
increase timeouts in niietcm4_opstatus_check() and niietcm4_uopstatus_check()
cause there were problems in some hardware configurations.
JTAG ID:
wrong id in k1921vk01t.cfg replaced with right one.
Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru>
Change-Id: I84296ba3eb4eeda4d4a68b18c94666f1269a500f
Reviewed-on: http://openocd.zylin.com/3171
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use it to print the manufacturer of detected TAPs
Change-Id: Ic4384c61c7f6f7ae2a9b860a805a5997542f72cc
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3177
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
dap_sync() executes all commands in the JTAG queue and then checks
if a WAIT condition happened inside the last batch. If yes, a recovery
is invoked. If not, processing continues without checking for
errors. This function should be called in long AP read or writes, e.g.
while uploading a new application binary, at intermediate points within
the transfer where the cost of flushing the JTAG queue and checking the
journal doesn't affect performance too much.
Change-Id: I99eeaf47cdf951e15e589a04e74b90b5ce911386
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3181
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
ADIv5 specifies that DP and AP accesses may generate a WAIT
response when the hardware is not able to complete a request for various
reasons in time before the next request is sent. Currently, the software
treats a WAIT response as a fatal error and aborts operation on the DAP.
This patch implements WAIT handling by keeping a journal of all
outstanding and completed accesses, including their response status.
At certain times (when dap_run() is called), the journal is inspected
for WAIT responses and all discarded accesses are replayed to complete
them. Special care is taken to not re-execute already successfully
completed operations.
Change-Id: I2790070388cf1ab2e8c9a042d74eb3ef776aa583
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3166
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Make the J-Link driver handle everything needed for FPGA programming,
this includes arbitrary long scans and STABLECLOCKS command.
Also, bump to the latest upstream libjaylink to properly support this.
This code is heavily inspired by Andreas Fritiofson's ftdi.c.
Change-Id: Ic5fd87aa88b58ff1138dc2e0a197bb52321b1541
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2946
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
BeagleBone debian 7 builds produce:
jlink.c: In function 'jlink_speed':
jlink.c:218:11: error: declaration of 'div' shadows a global declaration [-Werror=shadow]
jlink.c: In function 'check_trace_freq':
jlink.c:1065:54: error: declaration of 'div' shadows a global declaration [-Werror=shadow]
jlink.c: In function 'config_trace':
jlink.c:1101:11: error: declaration of 'div' shadows a global declaration [-Werror=shadow]
Fix this by changing the local variable to 'divider'.
Change-Id: I96a0cc0f7d4d4af5a56aa1e918e5416d3c61cbfe
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/3185
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
BeagleBone debian 7 builds produce:
adi_v5_jtag.c: In function 'jtag_ap_q_bankselect':
adi_v5_jtag.c:336:11: error: declaration of 'select' shadows a global declaration [-Werror=shadow]
Fix this by changing the local variable to 'sel'.
Change-Id: I8e29662ac12bc77d38d5064046d59b7364853cd9
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/3184
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The existing arm_adi_v5.c code decodes CoreSight peripherals based
on the part number field. However, these are specific to a
particular manufacturer (often ARM). The same part number from
two different manufacturers (distinct designer ids) should not
decode as the same CoreSight peripheral.
The Analog Devices ADSP-SC58x and ADSP-BF70x have peripherals that
overlap with existing OpenOCD decoding. The part number is the
same as existing OpenOCD decoding, but have a different JEP106 code.
Most, if not all, of the existing part number entries in
arm_adi_v5.c are probably specific to ARM. Change all entries
suspected to be designed by ARM to match only ARM's designer ID.
However, to preserve legacy behavior, existing non-ARM entries are
encoded with a wildcard so that they will behave in the same way as
the existing legacy code. It is desirable, however, to start
encoding the data with designer codes to avoid such ambiguity.
Revising the code to check both the part number and designer id
seemed to a warrant a const array lookup table instead of a
multi-tiered switch statement.
Also try to sync part identification IDs with relevant ARM docs.
Change-Id: Iac1374e4cfc6f04cebb479c0e3fa9bde527cc4a3
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
[andreas.fritiofson@gmail.com: change JEP106 to designer ID, cleanup]
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3128
Tested-by: jenkins
The HLA target shares an examine handler with cortex_m but since it
lacks direct access to DAP, some operations need to be omitted.
Change-Id: Ifdd9d3da4a3a3c2e1c9721284b21d041b3ccaa7a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3183
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
work around issues with software breakpoints when the text segment
is mapped read-only by the OS. Set DACR to "all-manager" to bypass
TLB permission checks on memory access.
Change-Id: I79fd9b32b04a4d538d489896470ee30b26b72b30
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3107
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change tests when reading from 'value' in sysfs from =='0' to !='1'.
This guards against broken sysfs GPIO implementations that return
non-zero for high rather than just '1' while still being clean and
correct code. Note that sysfs will never output a leading zero even
in a very broken implementation as that is covered in gpiolib.c, not
the offending driver.
Tested against broken Freescale kernel 3.14.38 on i.MX6SL.
Change-Id: Id05567bb8504b1babef33d6ee5172bceefeca8b8
Signed-off-by: Matthew Campbell <mcampbell@izotope.com>
Reviewed-on: http://openocd.zylin.com/3121
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On JTAG, all reads are pipelined. If you read a register, the result is not
delivered inside the request that issued the read, it is delivered in the
following request. The current code therefore issues a scan of the RDBUFF
register after each read. This adds a superfluous transaction after each
read.
This patch follows a strategy similar to what SWD already implements.
It also leverages that all JTAG reads are pipelined, i.e. the result
will be clocked out in the next JTAG data phase, no matter if it's
READ or WRITE. Therefore it's never necessary to explicitly read RDBUFF
other than for the very last READ before a dap_run().
Change-Id: Ie40b1fef3203f0cdcb503f40dcbd2a68b0f9776c
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3167
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Debug initialization blindly selects AP#0 as default, which is the AHB-AP
in many cases. This sets the default for target_read/write functions.
However, AHB-AP is the wrong choice, because it bypasses caches on read
and write and also makes some peripherals inaccessible (e.g. l2 outer
caches). This patch explicitely selects the APB-AP (debug_ap) as the
default.
Change-Id: I13f9e0750186d35dcfc135c8d67d437c5884d9c4
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3113
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Remove entirely the concept of a "selected" AP that has to be maintained
between calls. All the information the DAP ops need are now provided to
each call through the AP/DAP pointer.
Consolidate the cache of the SELECT fields into one single field caching
the entire register.
Change-Id: I2e1c93ac5ee8ac38a7d680ca2c660c30093a6b87
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3165
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Move the mandatory dap_ap_select() call into the dap_queue_ap_read/write
wrapper.
This avoids the need for dap_ap_select() and the notion of a "current" AP
within target code.
Change-Id: I5cde8f3eef2c662f7458be6f3b3dd44ea693bd74
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3164
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Make dap apsel without arguments show current state instead of changing
to AP 0.
Change-Id: I75ea10e3e1b8a067f2dc417ec6691dc7ceec1af6
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3163
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
All AP operations should select the AP to use before calling it so
there's no point in restoring the previous value afterwards.
The explicit call to dap_ap_select() before all AP operations should be
moved into dap_queue_ap_read/write() which then would have to take the
AP as an argument instead of the DAP.
Change-Id: Icacb0c76ef2a5ac36b4d2f26b52ec01a8850286e
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3156
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
It's currently set during target creation but the AP that will be used
for the target is not even known.
Change-Id: I4502e7eb1fa8d90f746445b8cf8a4c21cb7d519e
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3155
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The AP for which the TAR/CSW is printed may not be the one that caused
the failure. Remove the flawed output entirely. The correct info is
printed in mem_ap_read/write anyway.
Change-Id: I97580a0662dcf02e80646e45445cdbfc251122d8
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3154
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
All mem_ap_* functions now make sure the SELECT register is updated with
the AP number that it's operating on. This shouldn't have to be handled
explicitly.
Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This function does two separate things, powering up the DP and setting
up a MEM-AP. But the DP needs to be powered before even searching for a
MEM-AP to initialize and targets may have multiple MEM-APs that need
initializing.
Split the function into dap_dp_init() and mem_ap_init() and change all
call sites to use the appropriate one.
Change-Id: I92f55e09754a93f3f01dd8e5aa1ffdf60c856126
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3151
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reduce use of magic numbers and add AXI type MEM-AP detection. Don't try
to call dap_rom_display on a non-existent AP.
AP identification is unique per designer, so make sure the JEDEC code
matches ARM when interpreting the AP type.
Change-Id: I8e86b7de61811382afe99bf15094ab71b43f5fdf
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3150
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Change the debug_ap and memory_ap fields of the cortex_a target and
the debug_ap field of the cortex_m target to be pointers to the
struct adiv5_ap instead of AP numbers in some known DAP.
This reduces the dependency on the DAP struct in the targets and
enables MEM-AP accesses to take the relevant AP as parameter.
Change-Id: I39d7b134d78000564b7eec5bff464adf0ef89147
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3147
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This required fixing the AP ID parsing in dap_find_ap() to
match IHI0031C. The AXI type was added too.
Change-Id: I44577a7848df37586e650dce0fb57ac26f5f858c
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3146
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This will make it possible to reference directly the AP used for debug
in the target instance and remove the DAP reference. This will in turn
enable getting rid of the need to select an "active" AP in the DAP (using
dap apsel).
Change-Id: I265846a427c714204f4fd3df3cdb75843686c2d0
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3144
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Not clear what it was supposed to be used for. It probably shouldn't.
Change-Id: Ife1d833e59ba80f93876447d752a0ca7e7b57b0f
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3143
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be
able to pass a pointer to it to one common JTAG function which anyway
only uses the TAP field.
Refactor the function to take a TAP directly, remove the legacy struct
from cortex instances and store the TAP pointer only in the DAP.
Cortex-M makes a call to arm_jtag_setup_connection() with the struct
but the function does nothing useful for a Cortex-M target so remove
the call.
Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3142
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Making the SWD driver aware of the DAP that controls it is a layering
violation.
The only usage for the DAP pointer is to store the number of idle cycles
the AP may need to avoid WAITs. Replace the DAP pointer with a cycle
count hint instead to avoid future misuse.
Change-Id: I3e64e11a43ba2396bd646a4cf8f9bc331805d802
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3141
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Separate out the values from adiv5_dap that are associated with a specific AP into a new struct, so we can properly support multiple APs. Remove the DAP struct from the armv7* structs, because we can have multiple CPUs per DAP, and we shouldn't have multiple DAP structs. Tidy up a few places where ap_current is used incorrectly.
Change-Id: I0c6ef4b49cc86b140366347aaf9b76c07cbab0a8
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/2984
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Prepare to support multiple cortex-m cores on one DAP. Uses mem_ap_sel_*
functions and removes mem_ap_* functions. Adds a new debug_ap
parameter to the cortex_m (currently set to zero as in existing code).
Change-Id: I6926029d1e7bf44a42d453d1aff349bda824ba72
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/2983
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
ERROR_WAIT is better than ERROR_FAIL in timeout condition.
Change-Id: Iefe837f276a9091ce6c18db5947212c449f49d89
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2934
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is a TODO in the src/target/arm_adi_v5.h for MEM-AP registers.
Some new registers are introduced in ADIv5.2 specification.
MEM_AP_REG_MGT (0x20) // Memory Barrier Transfer register
MEM_AP_REG_TAR64 (0x08) // Bits[63:32] of Transfer Address
MEM_AP_REG_BASE64 (0xF0) // Bits[63:32] of Debug Base Address
Refer to
7.5 MEM-AP register summary in
IHI0031C: ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
Change-Id: I3bc4296a04c35f5c64f851e5865d3099922613fa
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2904
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Problem
No matter what target->coreid is, it always shows
Detected core 0 dbgbase: ...
In dap_lookup_cs_component(), it decreases the core index value to zero
in order to find the desired core.
The reference to coreidx is necessary considering "a device which has nested
ROM tables, with each core described in its own table." (by Paul Fertser).
Change-Id: I9b56d45d6edf6639e748a625ab27787f8e5a5776
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2902
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
They are only used to initialize the flash bank sectors and never modified.
Explicitly specify the array length while at it.
Cleanup before adding XMC4800 support.
Change-Id: I2985b9a9946b67798dbfd47d8b219d93a7ffc3da
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3131
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
cortex_a_read_apb_ab_memory_fast() uses the wrong order of ITR and DSCR
writes when setting up the transfer. ARM DDI0406C says in C8.2 regarding
"Fast mode" operation to first switch to fast mode and then latch the
instruction in ITR. Current implementation first wrote ITR, causing
the instruction to be executed immediately, then switched to fast mode
without an instruction latched. Repeated reading of DTRTX didn't
execute LDC and thus replicated its current content into the whole buffer.
This patch uses the following, revised algorithm:
1) switch to non-blocking mode and issue the LDC for the first word
2) if more than one word is to be read:
- switch to fast mode
- latch the LDC instruction into ITR (it is _not_ executed)
- issue (count-1) reads of DTRTX register, each read returns the current
content of DTRTX and re-issues the latched instruction
-> now the second-to-last word is in the buffer and the LDC for the last
word has been issued.
3) wait for the last instruction to complete
4) switch back to non-blocking mode
5) Read DTRTX for the last (or: only) word and put it into the buffer
Change-Id: I44f5c585962ffa5af257c3d5a2a802c122b6b1e4
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3122
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
When accessing memory through the ARM core, privilege levels and mmu
access permissions observed. Thus it depends on the current mode of the
ARM core whether an access is possible or not. the ARM in USR mode can
not access memory mapped to a higher privilege level. This means, if the
ARM core is halted while executing at PL0, the debugger would be
prevented from setting a breakpoint at an address with a higher privilege
level, e.g. in the OS kernel. This is not desirable.
cortex_a_check_address() tried to work around this by predicting if an
access would fail and switched the ARM core to SVC mode. However, the
prediction was based on hardcoded address ranges and only worked for
Linux and a 3G/1G user/kernel space split.
This patch changes the policy to always switch to SVC mode for memory
accesses. It introduces two functions cortex_a_prep_memaccess() and
cortex_a_post_memaccess() which bracket memory reads and writes. These
function encapsulate all actions necessary for preparation and cleanup.
Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3119
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
when disabling the mmu to access physical addresses, normally the d-cache
must be disabled as well. Disabling the d-cache also requires a full
clean&invalidate. However, since all memory writes are treated as write-
through no-allocate and memory reads do not allocate cache lines,
effectively the d-cache state does not change at all. We can therefore
save the the d-cache disabling and flushing.
This patch also simplifies the function a bit.
Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3114
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
for minimal impact on the hardware state, force all memory accesses to
bypass the caches and tlbs. This may actually be the default, but ARM
recommends in DDI0406C to set proper default values on debug init.
Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3079
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Other cache functions use an updated pattern for the address range loop.
Bring dcache clean and flush functions in line.
Change-Id: Iccb4a05c49054471033a3403363110cb08245d5b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3035
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint,
to make sure the d-cache is clean and invalid at the breakpoint
location down to PoC.
Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint
again, so that d-cache will pick up the modified code.
Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint
to memory to make the change visible to the CPU.
Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3033
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
D-Cache invalidate is a dangerous operation. It will only work correctly
if full cache lines are invalidated. When partial cache lines are
invalidated, i.e. the target address range does not start and end
at a cache line boundary, cpu data writes outside of the target range
will be dropped. This patch adds special treatment for partial cache
lines by doing a clean & invalidate on the partial lines before
invalidating the rest of the range.
Change-Id: I64099ddb058638e990a7eb0ee911b9cc8f6f8901
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3034
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The following changes are implemented:
- Clean&Invalidate the VA range to PoC *before* the write takes place
- Remove SMP handling since DCCIMVA instruction already maintains SMP
coherence.
- Remove separate Invalidate step
Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3027
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This patch adds a function for cleaning & invalidating a virtual
address range from the architecture caches down to the point of
coherence.
Change-Id: I4061ab023a3797fabc967f3a34498034841d52c6
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3026
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
There's only one function left that handles cache info display,
no need any more for a function pointer and runtime initialization.
Change-Id: I90b09577f81607917b11f0ab5600a0e2dce223e2
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3025
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
ARMv7 architecture allows up to 7 cache levels that are architecturally
visible, as opposed to "system caches", which are outside of the domain
defined by ARMv7 and require separate management. This patch enables
detection and identification of caches at all levels. It also implements
a new "flush-all" function that cleans & invalidates all cache levels to
the "Point of Coherence".
Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3024
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This patch is on the path to unified handlers for both inner and
outer caches. It removes the special overrides installed when
an outer cache is configured.
Change-Id: I747f2762c6c8c76c700341cbf6cf500ff2a51476
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3022
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The outer cache is not necessarily at L2 in a system. Rename functions
to make that clear.
Change-Id: Ia636a4844f50634f2bdf5cdce285febc1a47c11f
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3020
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch introduces, new command set and handlers for l1 and l2x caches.
Patch set 10 folded the following changes into this one:
Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415
If8d87a03281d0f4ad402909998e7834eb4837e79
I0749f129fa74e04f4e9c20d143a744f09ef750d8
Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/2800
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This was needed for ahb access
Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2796
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Problem
dap->ap_current is register value, not field value.
it restores invalid ap when it calls dap_ap_select(dap, ap_old) later.
* assume the current ap is 1, dap->ap_current value would be (1 << 24).
ap_old = dap->ap_current; <-- ap_old = 1<<24 = 0x1000000.
...
dap_ap_select(dap, ap_old); <-- select 0x1000000, not 1.
* All AP registers accessing fail afterwards.
One of the reproducible case(s): CORE residents in AP >= 1
dap_lookup_cs_component() being used to find PE(*).
In most cases, PE would be found in AP==0, hence the problem is hidden.
When AP number is 1, dap->ap_current would have the value of 1<<24.
Anyone get the AP value with dap->ap_current and resotre it later would
select the wrong AP and all accessing later would fail.
The ARM Versatile and/or FPGA would have better chance to provide this
kind of environment that PE residents in AP>=1. As they have an 'umbrella'
system at AP0, and main system at AP>=1.
* PE: Processing Element. AKA Core. See ARM Glossary at
http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014g/ABCDEFGH.html
Fix
Use dap_ap_get_select() to get ap value.
a. Retrieve current ap value by calling dap_ap_get_select();
src/flash/nor/kinetis.c
src/target/arm_adi_v5.c
b. The code is correct (dap->ap_current >> 24), but it's better to use
dap_ap_get_select() so everything could be synchronized.
src/flash/nor/sim3x.c
Change-Id: I97b5a13a3fc5506cf287e299c6c35699374de74f
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2935
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
If supported, the maximum transport speed is now retrieved from the
device.
Change-Id: I614f405ec91cf199c851781785fd26cbd10c37a6
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2955
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch uses libjaylink which is a library to access J-Link
devices. As other tools which are not in the scope of OpenOCD also
need to access J-Link devices a library is used. A firmware upgrade
tool and an advanced configuration tool for J-Link devices are under
development.
Further versions of libjaylink will support additional features
OpenOCD could benefit from. This includes TCP/IP as additional
possibility to connect to J-Link devices as well as power tracing and
device internal communication. The latter is used to access
peripherals on some development boards (e.g EFM32 STK and DVK).
Integration of libjaylink is realized with a git submodule like
jimtcl. As libjaylink depends on libusb-1.0 only, no additional
dependency is introduced for OpenOCD.
All low-level JTAG and SWD implementations of the current driver are
left untouched and therefore no incompabilities are to be expected.
Improvements of this patch:
* Support for more USB Product IDs, including those with the new
scheme (0x10xx). The corresponding udev rules are also updated.
* Device selection with serial number and USB address.
* Adaptive clocking is now correctly implemented and only usable for
devices with the corresponding capability.
* The target power supply can now be switched without the need for
changing configuration and power cycling the device.
* Device configuration is more restrictive and only allowed if the
required capabilities are available.
* Device configuration now shows the changes between the current
configuration of the device and the values that will be applied.
* Device configuration is verified after it is written to the device
exactly as the vendor software does.
* Connection registration is now handled properly and checks if the
maximum number of connections on a device is reached. This is also
necessary for devices which are attached via USB to OpenOCD as
some device models also support connections on TCP/IP.
* Serial Wire Output (SWO) can now be captured. This feature is not
documented by SEGGER however it is completely supported by
libjaylink.
This patch and libjaylink were tested on Ubuntu 14.04 (i386),
Debian 7 (amd64), FreeBSD 10.0 (amd64) and Windows XP SP3 (32-bit)
with the following device and target configurations:
* JTAG: J-Link v8.0, v9.0 and v9.3 with AT91SAM7S256
* SWD: SiLabs EFM32 STK 3700 (EFM32GG990F1024)
* SWD: J-Link v8.0, v9.0 and v9.3 with EFM32GG990F1024
* SWD: XMC 2Go (XMC1100)
* SWD: XMC1100 Boot Kit (XMC1100)
* SWD: IAR Systems / Olimex Eval Board (LPC1343F)
* SWD: Nordic Semiconductor nRF51 Dongle (nRF51422)
* SWD: SiLabs EZR32 WSTK 6220A (EZR32WG330FG60G)
Except for Windows XP all builds are tested with Clang in addition to
GCC. This patch and libjaylink are not tested on OSX yet.
Change-Id: I8476c57d37c6091c4b892b183da682c548ca1786
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2598
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
http://support.code-red-tech.com/CodeRedWiki/DebugAccessChip
> Note that once you have recovered debug access to your MCU, then in most cases you should then modify your Debug Configuration to turn vector catch off again. If this is not done, then this can cause problems in some circumstances with some versions of the Code Red IDE. For example with NXP LPC13xx parts, connecting more than once to the MCU with vector catch enabled can lead to the part ID being incorrectly read - which can again cause debug connections to fail
This patch adds an alternative part ID for LPC1343. With this patch "program" command works fine for flashing.
Change-Id: I8632e898a4c33102455925d25715b4f4edfa1d97
Signed-off-by: Jakub Kubiak <jakub@kubiak.es>
Reviewed-on: http://openocd.zylin.com/2782
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This adds docs, example config, flash driver.
Driver is only supports K1921VK01T model for now.
Change-Id: I135259bb055dd2df1a17de99f066e2b24eae1b0f
Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru>
Reviewed-on: http://openocd.zylin.com/3011
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The probe and info methods had duplicate sections decoding family names
to generate a human friendly part name. Extract this to a common
helper.
Change-Id: I4c6309d83c601e154b7c14ad9c15c53854ee1e98
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2932
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Basic basic support to get running, magic numbers taken from revision
0.90 of the reference manual.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Change-Id: Iff6ab94d30698f056ef09f7a856b7285fed8f441
Reviewed-on: http://openocd.zylin.com/2931
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
By saving a pointer to the tail of the list,
we don't need to traverse the entire command
queue before we're able to append an item to
it.
With this patch, I see a 10% improvement when
using the embedded XDS100v2 on AM437x IDK board
to load a 4MiB binary (linux zImage) to DDR
with load_image.
IOW, we went from ~305kB/sec to ~336kb/sec.
Change-Id: Idb55d49f0d0106043374ab520b2f3b6b32f2c50f
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2709
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Daniele Emancipato <daniele12457@hotmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The svf_progress_enabled variable is global, hence its lifetime is not
limited and it retains the value from the previous run. Fix this by
explicit assignment.
Change-Id: Id6f4fa88f39521606342a37f6876a0948ac5406e
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3111
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This makes SVF error output match actual line numbers in the file
processed.
Change-Id: I1fa4b9d0891e4358b7beada516945d5331ebe182
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2945
Tested-by: jenkins
Kinetis driver checks MDM STAT register to detect secured state of MCU.
An unsecured clean device typically triggered a huge fat alarm message.
Now when driver detects secured state it tries to halt MCU and then
re-reads status register.
Command "mdm mass_erase" used to deassert reset when finished
and MCU started looping in hard fault - WDOG reset cycle.
Now "reset halt" is issued. Clean flash is not run after mass_erase.
Change-Id: I23f393509fbd8751d44ffc744ff2d67f1074f74e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3010
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
SAMD driver suffered from following problems:
1) Flash was erased as an integral part of flash write.
It was not documented so with usual workflow it resulted
in erasing flash twice (and reducing flash lifespan)
and in almost double flashing time.
2) Sector erase was silently skipped if "is_erased" flag was set.
"is_erased" logic was not reliable, e.g. when a row write
was aborted after successful write of some pages, sector was
still considered as erased. "is_erased" flag could not
cope with flash writes from a user program.
3) Writing of a block with start address unaligned to a flash page
resulted in failed assert and OpenOCD abort.
4) Disabling cache in bit 18 of 16-bit halfword never worked.
MCU implements cache invalidate in hardware so there is no need
to take care about. This bug was reported by Tony DiCola.
New code does not erase flash in write operation.
Instead it traditionally relies on erasing flash beforehand.
"is_erased" logic and cache disabling is completely removed.
It simplifies write procedure a lot and flash write is now faster.
The change partly solves ticket #109 SAMD/SAM4L driver doubles flash erase.
Change-Id: I582b497d01a351575533a1f8c9810a4413be0216
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3045
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds support for the Atmel SAML21 variant B parts.
There is minimal change between the two variants, but in
variant B the automatic page write which the at91samd flash
driver relies on to be enabled is disabled by default.
With this patch the write row function will now issue a page write
command after each of the four pages in the row if the MANW (manual
write) bit is set. This also fixes flash write for the SAMC20/SAMC21
devices which have the MANW bit set by default as well.
I have also moved the device ID (DID) register bitfield extraction
from the find_part into helper macros. These can be used in the future
if there are more workarounds for specific devices.
Tested (programming) on:
ATSAML21-XPRO
ATSAML21-XPRO-B
SAMC21 Xplained Pro
SAMD21 Xplained Pro
SAMD20 Xplained Pro
Change-Id: I401a8aa1efd64730840c0d62cf49a1e880ea5900
Signed-off-by: Andreas Loehre <alohre@gmail.com>
Reviewed-on: http://openocd.zylin.com/2903
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cmsis-dap protocol has both DAP_Connect and DAP_Disconnect commands.
Logically if cmsis_dap_swd_switch_seq() calls DAP_Connect in connected
state it should call DAP_Disconnect first.
Doing so surprisingly solves problems on Atmel EDBG with target SAMD/R/L/C.
Without this change SWD communication breaks after reset run/halt
in config "reset_config srst_only" and reconnect trials repeatedly
fail with "SWD ack not OK: 0 JUNK"
Change-Id: Ie951098d5e0c83f388e2df414608aaabec2135c9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3098
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Atmel introduced a "Device Service Unit" (DSU) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Function is similar to SMAP in ATSAM4L, see http://openocd.zylin.com/2604
Atmel's EDBG adapter handles DSU reset correctly without this change.
An ordinary SWD adapter leaves TCK in its default state, low.
So without this change any use of sysresetreq or srst
locks the chip in reset state until power is cycled.
A new function dsu_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and DSU reset is released then.
Additionally SWD clock comment is fixed in at91samdXX.cfg and clock is
lowered a bit to ensure a margin for RC oscillator frequency deviation.
adapter_nsrst_delay 100 is commented out because is no more necessary after
http://openocd.zylin.com/2601
Change-Id: I42e99b1b245f766616c0a0d939f60612c29bd16c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2778
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
According to Infineon, XMC4500 EES AA13 with date codes before GE212 -
as seen on an XMC4500 General App Kit - had a zero SCU_IDCHIP register.
Handle this by extending our checks to not error out on zero SCU_IDCHIP
and by printing a useful info string in that case.
Change-Id: Ic2d641a314627dd5a1ff775a0113999191b95e3d
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2751
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
This is a complete flash driver for the Infineon XMC4xxx family of
microcontrollers, based on the TMS570 driver by Andrey Yurovsky.
The driver attempts to discover the particular variant of MCU via a
combination of the SCU register (to determine if this is indeed an
XMC4xxx part) and the FLASH0_ID register (to determine the variant).
If this fails, the driver will not load.
The driver has been added to the README and documentation.
Tests:
* Hardware: XMC4500 (XMC4500_relax), XMC4200 (XMC4200 enterprise)
* SWD + JTAG
* Binary: 144k, 1M
Note:
* Flash protect only partly tested. These parts only allow the flash
protection registers (UCB) to be written 4 times total, and my devkits
have run out of uses (more on the way)
Future Work:
* User 1/2(permalock) locking support via custom command
* In-memory flash loader bootstrap (flashing is rather slow...)
Change-Id: I1d3345d5255d8de8dc4175cf987eb4a037a8cf7f
Signed-off-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2488
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is a driver for the Atmel Cortex-M7 SAMV, SAMS, and SAME.
I started with the at91sam4.c driver and then restructured it
significantly to try to simplify it and limit the functionality
to just a flash driver, as well as to comply with the style guide.
Change-Id: I5340bf61f067265b8ebabd3adad45be45324b707
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/2952
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 68101e67ac introduced a
regression which resulted for ever-growing registers list (as output
by "reg" command), its contents were doubled every reset (actually,
every examination).
Change-Id: Ie3409c795160a2fc840a5e8a892928df0bcc0c57
Reported-by: Daniele Emancipato <daniele12457@hotmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3100
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This patch brings the calculation of the address ranges handled by
ttbr0 and ttbr1 registers in line with ARM DDI 0406C, Table B3-1
Change-Id: Ib807c4b1cb328a6f661e1a0898e744e60d3eccac
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3006
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
If ttbcr is changed after the debugger has examined a target for the
first time, address translations may fail. This problem does not show up
with Linux because it doesn't use ttbr1, but it shows with other OS that
use this feature. If the debugger connects to the target while it's in
u-boot, all address translations will fail after the OS has booted and
the target can not be debugged.
This patch reads the ttbcr in armv7a_mmu_translate_va() and compares it
a cached value. If a difference is detected, armv7a_read_ttbcr() is called
to re-parse the ttb configuration and update the cache.
Change-Id: I1c3adf53ea9d748a0e1e3091d9581e5c43ed64e8
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3005
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
kinetis_write() with byte count not divisible by prog_section_chunk_bytes
computed wrong wc and therefore paded section chunk by some
random data instead of 0xff
Change-Id: Ic7c66d8a3ceacda9e611e98b9fbf943b8001774b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2994
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Kx devices with FTFA flash need the watchdog disabled when programming.
I tried to keep overhead as small as possible and re-use registers that
were already inquired (e.g. sim_sdid).
Change-Id: Ibc29a26ec34102d78a6c3920dd16f63e134a8f6f
Signed-off-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-on: http://openocd.zylin.com/2986
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This makes it easier to relocate the install tree of OpenOCD from where
it was originally built (for example, if put onto a different machine),
without having to change scripts or add something to the command line
every time.
Change-Id: Ia5edf0eba166f7a999f267bd6a92402dab9b399e
Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3004
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The memory leak occurs when opening a file fails. It can be
reproduced by using the "flash verify_bank" command with a filename
that does not exist.
Change-Id: I60b7b545c18793d750ff75d08124fde3f0aa6f64
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2998
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If we work on smp system, the output of step command will depend
on Id of default target.
This patch adds additional information to help find what on which
core is happening.
Example of LOG after this patch.
imx6.cpu.1: target state: halted
^^^^^^^^^^
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x60000093 pc: 0x80076c0c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
imx6.cpu.0: target state: halted
^^^^^^^^^^
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x20000193 pc: 0x802ccb6c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
Change-Id: I536a2cce33b5ab10af9de2a43b9960320c17729f
Signed-off-by: Oleksij Rempel <external.Oleksij.Rempel@de.bosch.com>
Reviewed-on: http://openocd.zylin.com/2691
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A segmentation fault in cortex_m_endreset_event() is sometimes raised
with very broken target like Kinetis Kx with erased flash and active WDOG.
Debugging revealed that cortex_m->dwt_num_comp is 4 and
dwt_list is NULL at cortex_m:290
Change-Id: I229c59d6da13d816df513d1dbb19968e4b5951e2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2989
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Memory for the symbol table was allocated by malloc but not initialized other
than with the symbol name. Therefore `address` and `optional` members were
having arbitrary values leading to every symbol being optional most of the
time which messes up RTOS auto-detection. Memory will now be zero-initialized
as in other RTOS implementations.
Change-Id: I6c6e31ec1ef7e043061adf8c695b2139620e005d
Signed-off-by: Daniel Krebs <github@daniel-krebs.net>
Reviewed-on: http://openocd.zylin.com/3017
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
According to "man 2 poll" the correct header to include is poll.h, not
sys/poll.h. Reported by a build against musl.
Change-Id: I5298b49dc947d1a368e423104c0c0c7b9bdd1a10
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2947
Tested-by: jenkins
In the case that the STKALIGN bit is set on Cortex M processors, on
entry to an exception - the processor can store an additional 4 bytes
of padding before regular stacking to achieve 8-byte alignment on
exception entry. In the case that this padding is present, the
processor will set bit (1 << 9) in the stacked xPSR register. Use the
new calculate_process_stack callback to take into account the xPSR
register and use it on the standard Cortex_M3 stacking.
Note: Change #2301 had some misinformation regarding the padding. On
Cortex-M the padding is stored BEFORE stacking so xPSR is always
available at a fixed offset.
Tested on a Cortex-M0+ (Atmel SAMR21) board which has STKALIGN fixed
to a '1' such that this alignment always occurs on non-aligned stacks.
Behavior of xPSR verified via the (bad-sorry) assembly program below by
setting a breakpoint on the SVC_Handler symbol. The first time
SVC_Handler is triggered the stack was 0x20000ff8, the second time
SVC_Handler is triggered the stack was 0x20000ffc. Note that in both
cases the interrupt handler gets 0x20000fd8 for a stack pointer.
GDB exerpt:
Breakpoint 1, 0x000040b6 in Reset_Handler ()
(gdb) hbreak SVC_Handler
Hardware assisted breakpoint 2 at 0x40f8
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$3 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40ce 0x21000000
0x20000ff8: 0x0
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$4 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40e8 0x21000200
0x20000ff8: 0x0
Assembly program:
.cpu cortex-m0plus
.fpu softvfp
.thumb
.syntax unified
.section .vectors
@ pvStack:
.word 0x20001000
@ pfnReset_Handler:
.word Reset_Handler + 1
@ pfnNMI_Handler:
.word 0
@ pfnHardFault_Handler:
.word 0
@ pfnReservedM12:
.word 0
@ pfnReservedM11:
.word 0
@ pfnReservedM10:
.word 0
@ pfnReservedM9:
.word 0
@ pfnReservedM8:
.word 0
@ pfnReservedM7:
.word 0
@ pfnReservedM6:
.word 0
@ pfnSVC_Handler:
.word SVC_Handler + 1
.section .text
.global Reset_Handler
Reset_Handler:
cpsie i
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear
subs r2, r2, #4
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear2:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear2
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
.loop:
b .loop
.align 4
.stack_start:
.word 0x20000f00
.stack_last:
.word 0x20000ffc
@ first call - 0x2000fff8 -- should already be aligned
@ second call - 0x2000fffc -- should hit the alignment code
.global SVC_Handler
SVC_Handler:
bx lr
Change-Id: Id0940e6bbd6a59adee1378c0e86fe86830f0c8fc
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Paul Fertser <fercerpav@gmail.com>
Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Cc: Evan Hunter <evanhunter920@gmail.com>
Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3003
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Some targets (Cortex M) require more complicated calculations for
turning the stored stack pointer back into a process stack pointer.
For example, the Cortex M stores a bit in the auto-stacked xPSR
indicating that alignment had to be performed and an additional 4
byte padding is present before the exception stacking. This change
only sets up the framework for Cortex-M unstacking and does not
add Cortex-M support.
Note: this also fixes the alignment calculation nearly addressed by
change #2301 entitled rtos/rtos.c: fix stack alignment calculation.
Updated calculation is in rtos_generic_stack_align.
Change-Id: I0f662cad0df81cbe5866219ad0fef980dcb3e44f
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Paul Fertser <fercerpav@gmail.com>
Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Cc: Evan Hunter <evanhunter920@gmail.com>
Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3002
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Intel is relicensing our contributions to OpenOCD under GPL
version 2 or any later version. We previously contributed code
under GPL version 2 only. It was not our intention to differ
from the standard OpenOCD license. We're correcting that here.
This also applies retroactively to previous versions of our
contributions to OpenOCD.
Change-Id: I5e831ed95d03d2044d8e5a8375b21c6e52c933d7
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3044
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
K22FN1M0 and K22FX512 has FTFE flash and old style SDID.
K22FN128, 256 and 512 has FTFA flash and new style SDID
K63 and K64 detects as K61 and K62, see Errata 1N83J e7534
Change-Id: I2aca6f1f18819bb2b2ec4982036510de444ad2ac
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2867
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Patrick Stewart <patstew@gmail.com>
max_flash_prog_size euals to pflash_sector_size_bytes for most of devices.
There is no point setting max_flash_prog_size for devices without
FS_PROGRAM_SECTOR capability.
Check for zero sector_size to avoid div by zero exception in case of
device has FlexNVM but the driver does not define nvm_sector_size_bytes
Change-Id: Iaf4e007fb1ec3d24c373350410e4bebe504a4c3e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2958
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Patrick Stewart <patstew@gmail.com>
The K24 uses the KL-style SDID register and has some flashing quirks, so the kinetis driver does not support it properly.
Extend the chip detection routine to support the new SDID format. Add a parameter for the maximum flash size, as the K24 only supports 1k flashing blocks but has 4k sector size. Remove global 'granularity' array, as it's only really needed in one function. Replace 'klxx' with an enum showing which flash commands are actually supported on a given chip.
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Change-Id: Ie244fab564d58c5cfe4fa36a025f0b2674ffad69
Reviewed-on: http://openocd.zylin.com/2864
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I3cf5ced568319878b8bf40743e4c07718f630c68
Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2953
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Flash driver "mini51.c" and "nuc1x.c" are same target MCU.
This patch integrates each driver and functions,
and makes into new "NuMicro" flash driver.
Change-Id: Ifff5c1cfdd265acca0f489631695be9194fa144c
Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/2794
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A target config and a simple flash driver for the ADuCM360 microcontroller.
The EEPROM of the chip may be erased and programmed.
Change-Id: Ic2bc2f91ec5b6f72e3976dbe18071f461fe503b8
Signed-off-by: Ivan Buliev <i.buliev@mikrosistemi.com>
Reviewed-on: http://openocd.zylin.com/2787
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
The problem was reported by jstefanop on IRC, the SVF was generated with
Xilinx ISE 14.7.
Found and investigated with Valgrind's vgdb service.
Change-Id: I32b0e77e0380ce4a391661f97449f9c2a5f83625
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2933
Tested-by: jenkins
Currently, the maximum size of a command sent to the TCL server is
4k. This patch increases this limit up to 4M.
Reasoning:
To get high-speed JTAG data transfers, I'm using a very long shift
register. This reduces the overhead of the state changes, as well as the
latency due to the common USB adapter transfers considerably. In order
to submit those long DRSCAN commands to OpenOCD over the TCL/TCL
interface, long TCL command lines are required. This is enabled by this
patch.
v3:
Address review comments. Drop line instead of connection when realloc()
fails.
Changes in v2 of this patch:
The line buffer is allocated dynamically to avoid an OpenOCD memory
overhead if the large buffers are not used. The buffer starts at 4K and
increases exponentially up to 1M, and then linearly in 1M increments up
to 4M.
Change-Id: Iecaef6a56ed5e18e9de4d912a514031ea78fa3bd
Signed-off-by: Philipp Wagner <philipp.wagner@tum.de>
Reviewed-on: http://openocd.zylin.com/2837
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add constant CONNECTION_LIMIT_UNLIMITED which indicates a service
has no connection limit
Change-Id: I008d31264010c25fa44ca74eb6d5740eca38bee1
Signed-off-by: Austin Morton <austinpmorton@gmail.com>
Reviewed-on: http://openocd.zylin.com/2937
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Problem
As my compiler has "warnings being treated as errors" on, it shows the
error message:
error: 'retval' may be used uninitialized in this function
Investigation
Nothing wrong with the logic, 'retval' would have a value before returning.
Just wanna get rid of the compiling "warning as error" message.
Solution
Provide a reasonable default value
Change-Id: I712c15f82819c6c48bee9dceca8de4b18aeb29b0
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2905
Tested-by: jenkins
Reviewed-by: Robert Jordens <jordens@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
During reallocation a new memory region might be allocated and the old
one freed. If jtag queue is holding a pointer to the old memory, it will
segfault during the execution. Avoid this by flushing the queue before a
reallocation attempt is made.
This should fix ticket #102.
Change-Id: I737fc3f1ebf6d76413a475beb8bf20184fe0233f
Reported-by: Alex Forencich <aforencich@users.sf.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2899
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Added support for SWD transport similar to sysfsgpio driver.
Added configurable peripheral base address to support Raspberry Pi 2.
Change-Id: If76d45fbe74ce49f1f22af72e5f246e973237e04
Signed-off-by: Christoph Pittracher <pitt@segfault.info>
Reviewed-on: http://openocd.zylin.com/2802
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the chip IDs corresponding to the new 5V "SAMC" parts which are
otherwise identical to the SAMD and should work with this driver. Also
add the configurations for their Xplained Pro boards.
Change-Id: Ic268d4ac384a3a77d4211a94da9f9faf4d8c0f7b
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2809
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This fixes a warning as reported by the current clang version:
../../../../src/flash/nor/sim3x.c:867:20: error: address of array
'sim3x_info->device_package' will always evaluate to 'true' .
Change-Id: Ie160cbe6df8f491e9beff38d47e2f13575529bf9
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2838
Tested-by: jenkins
Reviewed-by: Oleksij Rempel
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Many FPGA board speak JTAG and have a SPI flash for their bitstream
attached to them. The SPI flash is programmed by first uploading a
proxy bitstream to the FPGA that connects the JTAG interface to the
SPI interface if the IR contains a certain USER instruction. Then the
SPI flash can be erase, written, read directly through the JTAG DR.
The JTAG and SPI signaling is compatible. Such a proxy bitstream only
needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the
chip select when the IR contains the special instruction and the JTAG
state machine is in the DR-SHIFT state.
Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2844
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The only read access to flash chips so is through the target's
memory. Flashes like jtagspi do not expose a memory mapped interface
to the flash. These commands use the flash_driver_read() driver API
directly.
Change-Id: I40b910de650114a3f676507f9f059a234377d862
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2842
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds an option to disable the use of the JSTART instruction
when loading bitstreams to xilinx fpgas. JSTART apparently prevents
configuration if the startup clock is not set to the jtag clock in
the bitstream.
xc3sprog is omitting JSTART for all devices. Problems with loading a bitstream
that does not have StartupClk:JTAGClk are described here:
http://www.xilinx.com/support/answers/56151.html
Change-Id: I8137c0bae05a8c3c6f8e2611869f70a770d1651d
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2860
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The testee target is usefull for certain non-cpu pass-through
situations, for example in the case of a spi flash mapped to the DR of
a JTAG tap, as is the case for most FPGAs with SPI flashs behind them.
We just manage the RUNNING/RESET/HALTED state in the testee driver to
support it being halted which is a requirement for flash banks.
Change-Id: I1b4d52c58a1f6bd753e126bfde74dcc5164d7b69
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2840
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
* Add USB VID and PID for the J-Link interface running on the Nordic
Semiconductor nRF51-DK. Also tested with debug out port to debug
external boards.
* Elimiantes need for `-c "jlink pid 0x1015"` on the openocd cmd line.
Change-Id: Ib23acb72b9f5183b76fc7dc22b556982869ae830
Signed-off-by: Kyle Manna <kyle@kylemanna.com>
Reviewed-on: http://openocd.zylin.com/2775
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
ThreadX uses two stacking schemas on ARM926E-JS, extend API to use more then
one stecking at time.
Change-Id: I92d445ad0981b6409ea4c4e7e438d3a7ae39cbe7
Signed-off-by: Alexander Drozdov <adrozdoff@gmail.com>
Reviewed-on: http://openocd.zylin.com/2848
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
MMU types were checking and installing fakes at init, but this wasn't catching
all devices. Fixes segfaults when attempting mdw and friends on avr.
Change-Id: I5b11f9913157a21f1aeb11ec852f593b529d9be8
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2791
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Even though the latest firmware version for stlink-v1 supports "v2"
JTAG API, the hardware SRST handling is still broken; amend the check
accordingly.
Change-Id: I62c662cd7aa209d2d6e9fe260f5c0be81d0ce672
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2761
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the identifiers to support the flash on the Cypress Type-C Port Controller
chips of the CCG1 family : http://www.cypress.com/ccg1/.
Tested successfully on CYPD1132-16SXI.
Change-Id: I3fe6283379e5bcab964afac31b547ef95535aa2c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://openocd.zylin.com/2757
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The notation Gx0 in the nRF51 Series Compatibility Matrix indicates that
the specified HWID is valid only for build code 0 of each chip, and for
subsequent builds the HWID will be different. Replace the Gx0 notation
with G0 throughout, and add the missing HWID for nRF51422 QFAC A1
(present on the newer nRF51 developer boards).
See: https://www.nordicsemi.com/eng/nordic/download_resource/41917/5/55913589
See: https://devzone.nordicsemi.com/question/30774/mapping-hwid-to-revision-information/
Change-Id: I79d842137d41342db35904867c48b06fbc6fbc70
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2593
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Since mqx comes last in the list, with the auto option its
update_threads is called even though it wasn't detected.
This check should be removed from all the rtos helpers and moved to
the generic code, but better do it later all in one go.
Change-Id: If24ab42a58a468d90e9f12028d4c2fb76a9bc2e8
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2741
Tested-by: jenkins
It was observed on AM437x that after every reset the target's debug
regions are unpowered. To be able to properly communicate with the
target and perform cortex_a init debug access after a reset event the
examination need to be performed every time, not just on OpenOCD
start.
Change-Id: Idf272e127ee88341e806ee00df154eade573451d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2723
Tested-by: jenkins
Reviewed-by: Felipe Balbi <balbi@ti.com>
After intermittent connection failures or target power failures it
might be necessary to try reexamination even when polling fails. This
should make communication with Cortex-A targets more reliable.
This was runtime tested with stlink attached to an stm32l1 and an FTDI JTAG
adapter attached to an stm32f1 target.
Change-Id: I38c4db8124b7f4bbf53ddda53c13273449f49c15
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2721
Tested-by: jenkins
Reviewed-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Färber <afaerber@suse.de>
This adds support for the new Atmel SAML21 family of low-power Cortex
M0+ devices. Their Flash controller is essentially the SAMDxx one so
the change consists of adding the new part IDs. Unfortunately the
device ID logic had a couple of mistakes in it that did not affect
anything on SAMD2x devices (due to 0 values expected there) but that is
a problem on L21, it's therefore addressed here and things should now
match the datasheets.
Tested on Amtel SAML21 Xplained Pro development kit against the included
SAML21J18A there. Also tested for regressions on a SAMD20 and SAMD21
using their dev kits.
Change-Id: I768f75e064b8656c15148730dacaa4c3acfc4101
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2690
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds the mandatory Info documentation for the driver as well as
the usage field.
As a clean up, this also includes freeing of the allocated memory
which results in a memory leak if probe is invoked multiple times.
Valgrind-tested.
Reported by Dmitry Shpak.
Change-Id: I2b1d9b9e8b069c6665b11d880b40ce19a1b26ce6
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2694
Tested-by: jenkins
Reviewed-by: Дмитрий Шпак <disona@yandex.ru>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch was tested with an EZR32WG Starter Kit.
Change-Id: I0f7c619e715fe30e88e6da3bead0806dd3bce819
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2700
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Run-time tested with FreeRTOS V8.1.2 (current version).
For the time being I propose this way of dealing with RTOSes that do
not export necessary information on their own.
I also suggest implementing a similar scheme for ChibiOS, exporting
the necessary struct fields' offsets via an OpenOCD-specific helper.
Change-Id: Iacf8b88004d62206215fe80011fd7592438446a3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2347
Tested-by: jenkins
xSuspendedTaskList and xTasksWaitingTermination are only available for
some configurations. Missing optional symbols will have their addresses
remaining at zero so the corresponding lists will be skipped when
building the task list.
Change-Id: If330f5038d009298c3a14a4d2756db7105a30bc8
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2425
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is a remake of http://openocd.zylin.com/1966
originally written by Angus Gratton <gus@projectgus.com>
ATSAM4L has a "System Manager Access Port" (SMAP) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Without this change any use of sysresetreq or srst locks the chip
in reset state until power is cycled.
A new function smap_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and SMAP reset is released then.
Change-Id: Iad736357b0f551725befa2b9e00f3bc54504f3d8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2604
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Some targets need arbitrary amount of time (usually not too long)
after reset (both sysresetreq and srst) to do initialisation, and
SWD/JTAG is not available during that. According to PSoC4 docs, the
debugger should try connecting until it succeeds.
Also ahbap_debugport_init might be necessary to perform after using
hardware srst too, so add it there (except for the targets that
support srst_nogate since they are very unlikely to need it).
Change-Id: I3598d5ff7b8e0bf3a5566a57dec4b0b2b243d297
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2601
Tested-by: jenkins
In some cases (the most obvious are TI's SoCs) ROM table lacks entries
for the cores, so OpenOCD has no way to determine what debug base to
use. Due to an error fixed in ec9ccaa288 it wasn't handled properly,
and OpenOCD would continue to try using dbgbase = 0, which happened to
work for e.g. AM437x.
This patch adds a clear indication to the user that to access such a
target, dbgbase must be set manually in the config.
Reported by Felipe Balbi on IRC.
Change-Id: Id8533e708f44b76550eb8b659564f5f45717c298
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2603
Tested-by: jenkins
In some circumstances (e.g. inappropriate jtag clock)
target_write_memory in lpc2000_iap_working_area_init might fail. The
allocated working area should be freed inside
lpc2000_iap_working_area_init in this error case.
This was leading to a weird segfault due to stack corruption later
when reset was executed.
Reported by quitte (Jonas Meyer).
Change-Id: Ia2ed42a9970a4d771727fd516a6eea88e9b859e2
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2696
Tested-by: jenkins
Calling ahbap_debugport_init() is wrong here because the actions
performed by it might lead to jtagdp_transaction_endcheck errors thus
leading to infinite recursion.
The removed code is not needed now because target polling should lead
to reexamination automatically, and both cortex_a and cortex_m call
ahbap_debugport_init() as part of their target examine handler.
This was reported as a real life issue on IRC by Weaselweb with
Cortex-A target. Quitte reports similar results in some circumstances
(adapter_khz too high) with LPC17xx.
Change-Id: I7148022f76a1272b5262d251f2e807ffb1543547
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2697
Tested-by: jenkins
The IAP working area needs to be freed here, just like in all the
other driver functions since an automatic local variable is used to
store a pointer to it.
This was reported by quitte (Jonas Meyer) on IRC as a strange totally
unrelated segfault after doing certain operations (leading to target
reset) from GDB. He has provided me with remote access to the specific
machine and configuration that exposed the issue, and after some
debugging it became apparent that a auto local variable (holding the
gdb connection pointer) gets overwritten somehow. Placing an
appropriate breakpoint just before the event and using a watchpoint
made the cause apparent: reset lead to freeing of all working areas,
and there was one holding a pointer to a variable that was auto local
in get_lpc2000_part_id().
Change-Id: I7e634d890135ca0f3b4b311e09e8385a03982bd6
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2695
Tested-by: jenkins
This regression was introduced with d90b86d8. "transport select" doesn't
throw an error anymore and autoselects the first available transport on
its own.
Reported by moyix on IRC.
Change-Id: I3f303c0372e915931cca4b28af450694abc1a63e
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2693
Tested-by: jenkins
The detection framework assumes rtos->symbols is dynamically allocated,
an assumption that the ChibiOS variant breaks by providing a raw statically
allocated symbol list.
Change-Id: I379bcc2af99006912608ddd3f646ff7085606f47
Signed-off-by: Richard Braun <rbraun@sceen.net>
Reviewed-on: http://openocd.zylin.com/2597
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch might influence openocd Tcl commands behaviour in subtle
ways, please give it a nice testing.
The idea is that if an OpenOCD Tcl command returns an error, an
exception is raised, and then the return code is propogated all the
way up (or to the "catch" if present). This allows to detect
"shutdown" which is not actually an error but has to raise an
exception to stop execution of the commands that follow it in the
script.
openocd_thread special-cases shutdown because it should then terminate
OpenOCD with a success error code, unless shutdown was called with an
optional "error" argument which means terminate with a non-zero exit
code.
Change-Id: I7b6fa8a2e24c947dc45d8def0008b4b007c478b3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2600
Tested-by: jenkins
Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Commit a35712a85c caused a regression where command
openocd -c "echo a1; shutdown; echo a2"
always returned non-zero exit status to operating system,
even when commands before shutdown all succeeded. This patch
attempt to fix this.
Change-Id: I3f478c2c51d100af810ea0171d2fd4c8fcc657f3
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Reviewed-on: http://openocd.zylin.com/2589
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Found by clang static checker.
On the very first call of jim_newtap_expected_id() pTap->expected_ids
and expected_len are null, and there's nothing to copy. This patch
changes this cryptic code to use realloc() instead.
Change-Id: Ic0b5140d08257a906f15b55a2ae64db7bc06d5f1
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2562
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Tested-by: jenkins
Current flash driver can fail to write across the sector boundary.
This patch fixes "thisrun_bytes" set to "cmd51_dst_boundary" value instead of "cmd51_can_xxxxb"
Referred to SevenW's post and fix,thanks.
http://sourceforge.net/p/openocd/mailman/openocd-devel/thread/fa32e7d6654df22470dc5f4a3dbc984a%40familiebenschop.nl/#msg33594152
Tested on below listed chips.
LPC810,LPC811,LPC812,LPC824,LPC1115,LPC1343,LPC1347,LPC1227,
LPC1769,LPC1788,LPC54102,LPC4088 and LPC2388.
Change-Id: If1c6a1daa58ca27c405bd959a784e599a7a8f4d4
Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/2607
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The original code had iterated 10,000,000 times and taken the elapsed
time divided by 10,000, to yield kHz which is mathematically correct
only if we were measuring time in seconds, but we are measuring time in
milliseconds, so the correct divisor is actually 10,000,000. Previous
code would report 0.500 for actual measured speed of 500 kHz.
Change-Id: Iba4c4961fe3973e7ccfa6dfa11d606a966ceb50c
Signed-off-by: Ed Beroset <beroset@ieee.org>
Reviewed-on: http://openocd.zylin.com/2573
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
When the SCTLR has C set but M unset (i.e. Caching on, but MMU off) the cache
if effectively off. So only flush the cache if MMU is on, otherwise stale
entries might be committed to memory.
Change-Id: Iaff8b6f25b7a41ba838b91d45684c98f99fc0b27
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/2429
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Vladimir Svoboda <ze.vlad@gmail.com>
Since SWD is currently abusing the JTAG command queue for reset and
sleep handling (and all other operations are performed in a different
way), sleep needs to be forced explicitly to ensure correct timings.
Change-Id: I5b0da6cbb7d0560154e4077b261aa6828cefc892
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2591
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Bug in read pointer check within flash write algorithm made incorrect check
if block size is more than 4 bytes (bug was detected with 16 bytes block size).
Change-Id: I5b8e7ebca619a0a85ae6e9e496ff792248134d81
Signed-off-by: DmitryShpak <disona@yandex.ru>
Reviewed-on: http://openocd.zylin.com/2657
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This should allow most of the existing configurations for older
versions to remain compatible without forcing the user to change his
or her config to explicitly select transport.
Also in some circumstances can remove the need to chain a "-c transport
select X" when building custom configs on the command line, which seems
like a common new user pitfall.
Change-Id: Ic87a38c0b9b88e88fb6d106385efce2f39381d3d
Suggested-by: Petteri Aimonen <jpa@git.mail.kapsi.fi>
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2551
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This brings SWD reconnection procedure in line with the ARM
documentation and changes cortex_m reset procedure to make use of it.
The motivation behind this patch is to make SAM4L "reset" and "reset
halt" properly without SRST. The complication here is that EDBG issues
an additional read of DP_RDBUFF automatically right after writing
SYSRESETREQ, that leads to a FAULT which needs to be dealt with
properly. With this patch the very first ahbap_debugport_init DAP
access will make SWD layer properly reinitialise the link before
continuing.
Runtime tested with mbed CMIS-DAP + KL25 only.
Change-Id: Ic506f9db30931dfa60860036b83f73b897975909
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2596
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Valgrind-tested.
Comparison of flashing performance on an FRDM-KL25Z board running mbed
CMSIS-DAP variant, 5MHz clock, old driver:
wrote 28096 bytes from file demo.elf in 26.833590s (1.023 KiB/s)
verified 27264 bytes in 1.754972s (15.171 KiB/s)
this implementation:
wrote 28096 bytes from file demo.elf in 3.691939s (7.432 KiB/s)
verified 27264 bytes in 0.598987s (44.450 KiB/s)
Also tested "Keil ULINK-ME CMSIS-DAP" with an STM32F100 target, 5MHz
clock, results reading from flash, old driver:
dumped 131072 bytes in 98.445305s (1.300 KiB/s)
this implementation:
dumped 131072 bytes in 8.242686s (15.529 KiB/s)
Change-Id: Ic64d3124b1d6cd9dd1016445bb627c71e189ae95
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2356
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Many kinetis parts come in multi-bank configuration, so this
optimisation here can't be performed safely.
Investigated and fixed by Richard Braun.
Change-Id: I2b56614b47951595c403a1a8edd3afe11b85679b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2594
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This provides support for various trace-related subsystems in a
generic and expandable way.
Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2538
Tested-by: jenkins
Avoids "J-Link hw type unknown 0x10" on the Infineon Relax Lite Kit.
Change-Id: I3091623ead2e84b67ac20d9866307ccbb3f26f66
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2568
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Avoids "J-Link hw type unknown 0x11" on various Infineon boards.
Change-Id: If20b9e21110d2acc02be57f5faf28c5e6a39e2c9
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2565
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This should facilitate dynamic target creation and removal.
Currently it helps with getting 0 bytes lost report from Valgrind on
exit (after talking to a nucleo board). However, 1,223,886 bytes in
5,268 blocks are still reachable which means the app holds pointers to
that data on exit. The majority comes from the jtag command queue,
there're also many blocks from TCL command registration.
Change-Id: I7523234bb90fffd26f7d29cdd7648ddd221d46ab
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2544
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
The target might be using Tcl examine-start and examine-end handlers,
they need to be called when the target gets reexamined after polling
succeeds again.
Change-Id: I371380c6f3c427ec7a0206d73426f6589f18a9bd
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2536
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
This bug was exposed by Valgrind.
Change-Id: I2e2bc036b49ca3ff22f78f765ee4537763350096
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2543
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This bug was exposed by Valgrind.
Change-Id: If50878664d928c0a44e309ca1452089c1ac71466
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2542
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Warning, behaviour change: before this patch if a timer callback
returned an error, the other handlers in the list were not called.
This patch fixes two different issues with the way timer callbacks are
called:
1. The function is not designed to be reentrant but a nested call is
possible via: target_handle timer event -> poll -> target events
before/after reexaminantion -> script_command_run ->
target_call_timer_callbacks_now . This patch makes function a no-op
when called recursively;
2. The current code can deal with the case when calling a handler
leads to its removal but not when it leads to removal of the next
callback in the list. This patch defers actual removal to consolidate
it with the calling loop.
These bugs were exposed by Valgrind.
Change-Id: Ia628a744634f5d2911eb329747e826cb9772e789
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2541
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
When target was already halted during the initial examination,
arm11_check_init() was trying to read, store and interpret DSCR
contents before the DPM structure is initialised. This caused
a segfault like described on
http://sourceforge.net/apps/trac/openocd/ticket/65 .
This is a totally untested attempt to fix this issue.
Change-Id: I2fff115679a3f0023e7a88c749ccb5f045d6cf01
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2043
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Otherwise it happens if stlink can not be opened on start.
Change-Id: I7088f10e61508dae230eccfe576a51498c92f5b8
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2550
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Stian Skjelstad <stian@nixia.no>
This is runtime and valgrind tested with l0, l1 and f3 hla boards.
Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2516
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds the fpv4-sp-d16 registers to the armv7m register set.
The work is inspired by Mathias K but takes a different approach:
instead of having both double and single presicion registers in the
cache this patch works only with the doubles and counts on GDB to
split the data in halves whenever needed.
Tested with HLA only (on an STM32F334 disco board).
Currently this patch makes all ARMv7-M targets report an FPU-enabled
target description to GDB. It shouldn't harm if the user is not trying
to access non-existing FPU. However, the plan is to make this depend
on actual FPU presence later.
Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a
Signed-off-by: Mathias K <kesmtp@freenet.de>
[fercerpav@gmail.com: rework to fit target description framework]
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/514
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Found by clang static checker.
Change-Id: I77b0dc18188328fdb28d07b9e5c52e06182d9e2b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2561
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Found by clang static checker.
Change-Id: Ifa58ba383092341c7343916e5cc8ec3c72ab2f60
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2560
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Found by clang static code checker.
Change-Id: Ic1370f8d7a48f08da6514afec5aacde38af7dfb6
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2559
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
ARMv7E-M (CortexM4) architecture
- fix position offset of r2,r3 registers on exception stack
- switch 'calloc' arguments
- remove prototypes of internal function and typedefs
- add NULL check for alloc functions
- remove last line of license "Franklin Street, Fifth Floor"
because of 'checkpatch' validation
- environment: jlink + twrk60n512
Change-Id: I70840ded15b17dd945ca190ce31e2775078da2d9
Signed-off-by: Marian Cingel <cingel.marian@gmail.com>
Reviewed-on: http://openocd.zylin.com/2353
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for the at90usb128 flash (tested on the RZUSBstick)
Change-Id: Ic042d7c403b20a5cc533da00c30ae6e2139bbd10
Signed-off-by: Olivier Esver <olg.esver@gmail.com>
Reviewed-on: http://openocd.zylin.com/2557
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Solution found on the internet
Change-Id: Ied6f7d9b28131a7ac83b203e4c64d4e9ffec0595
Signed-off-by: Mateusz Manowiecki <segmentation@fault.pl>
Reviewed-on: http://openocd.zylin.com/2496
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Failed build on Mac OS X 10.10.2 was reported in OpenOCD-devel.
Cleaning types and printf formats. uint32_t prefered for flash/sector sizes.
2 minor changes in comments.
Removed redundant bracket.
Change-Id: Ia06b77af59c2c0ffd10869a4b263a760ca8b0a7a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2558
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
Added new entries to the nrf51_known_devices_table array. New entries
are documented in the "nRF51 Series Compatability Matrix V1.0" found on
the Nordic Semi web site. Reordered entries to match the order found in
the document.
Also added an entry for an undocumented hwid discovered while flashing
the PCA10031 and PCA10028 dev boards.
Change-Id: Icca7da103d437dc28e651f27ab937fe953b9aac9
Signed-off-by: Theodore A. Roth <troth@openavr.org>
Reviewed-on: http://openocd.zylin.com/2514
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Given that the manual states that these two subcommands are
deprecated and were scheduled to be removed back in 2010,
remove them and the corresponding documentation from the
manual.
Change-Id: Iaac633349d7fcb8b7f964109c7d26dd0cc5fc233
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-on: http://openocd.zylin.com/1860
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Based on the initial work on bcm2835gpio.c by Paul Fertser with many
additions. Modifications to the GPIO handling was minimal in this
patch. A more big modification is required before cleanup the
interface between bitbang and sysfsgpio.
Change-Id: I54bf2a2aa2ca059368b0e0e105dff6084b73d624
Signed-off-by: Jean-Christian de Rivaz <jc@eclis.ch>
Reviewed-on: http://openocd.zylin.com/2438
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is based on the initial work by Paul Fertser with addition of the
switch sequences and new ACK handling. In case of WAIT response, the
sticky bits are cleared and the last operation is repeated. The ACK
handling is based on the interpretation of the 8 February 2006 ARM
Debug Interface v5 Architecture Specification
Change-Id: Id50855b1ffff310177ccf9883dc9eb0d1b4458c8
Signed-off-by: Jean-Christian de Rivaz <jc@eclis.ch>
Reviewed-on: http://openocd.zylin.com/2437
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
I couldn't make OpenOCD to work with GDB. I was always getting this in GDB:
(gdb) target remote localhost:3333
Remote debugging using localhost:3333
Ignoring packet error, continuing...
Ignoring packet error, continuing...
Ignoring packet error, continuing...
Ignoring packet error, continuing...
Malformed response to offset query, timeout
(gdb)
While debugging gdb remote protocol, I have seen that gdb responds with:
w ++$?#3f
And those two '+' seems to confuse the OpenOCD parser, if it sees another
'+' sign it emits the DEBUG output and sets the noack_mode to 2. The
problem is that we weren't even IN noack mode, this was set to 0 and then
it explicitly sets it to 2 and thus turning the noack mode on.
Change-Id: If267c9226e57fa83121ded09cf69829f8f0b4b93
Signed-off-by: Matej Kupljen <matej.kupljen@gmail.com>
Reviewed-on: http://openocd.zylin.com/2545
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Without this patch, to perform a memory read, OpenOCD first issues an
LDC instruction into DBGITR in Stall mode (thus executing the
instruction), then switches to Fast mode and reads from DBGDTRTX once
for each word to transfer.
At the very end of the transfer, the final Fast mode read of DBGDTRTX
has, as always, the side effect of re-issuing the LDC instruction. This
causes two problems:
(1) If the word immediately beyond the end of the requested region is
inaccessible, this spurious LDC will cause a fault. On a fast CPU, the
LDC will finish executing by the time the poll of DSCR takes place,
failing the entire memory read. On a slow CPU, the LDC might finish
executing later, leaving an unexpected and confusing sticky fault lying
around for the next operation to see.
(2) If the LDC succeeds, it will leave the loaded word in DBGDTRTX, thus
setting DBGDSCR.TXFULL=1. The cortex_a_read_apb_ab_memory routine
completes without consuming that last word, thus confusing the next
routine that tries to use DBGDTRTX (this may not have any visible effect
on some implementations, because writing to DBGDTRTXint when TXFULL=1 is
defined as Unpredictable, but I believe it caused a visible problem for
me).
With this patch, the bulk mem_ap_sel_read_buf_noincr is modified to omit
the last word of the block. The second-to-last read of DBGDTRTX by that
function will cause the issue of the LDC for the last word. After
switching back to Normal mode and waiting for that instruction to
finish, do a final read of DBGDTRTX to extract the last word into the
buffer, leaving TXFULL=0.
Without this patch, memory accesses are always expanded such that they
are aligned to the access size. With this patch, accesses are issued
exactly as ordered by the caller. The caller is expected to handle
fragments at the beginning and end of the transfer if the address is
unaligned and an unaligned access is not desired.
Without this patch, the DFAR and DFSR registers, which report the
location and status of data faults, are ignored while performing memory
accesses, which could cause problems debugging an OS page fault handler.
With this patch, DFAR and DFSR are preserved across memory accesses, and
DFSR is decoded in the event of a synchronous fault to provide the
caller with more information about the reason for failure.
Thanks to Boris Brezillon for the original patch whose ideas led to the
non-word access mechanism implemented here and to various code reviewers
for their comments.
Change-Id: I11ae7104fbe69a522efadefc705c9a217a7eef41
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/2381
Tested-by: jenkins
Reviewed-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
RM0038 Rev.12 lists these new parts and introduces the category naming
scheme.
RM0367 Rev.2 (STM32L0x3 RM) doesn't add any new codes.
Change-Id: Id95dd48dda64d5f108dac57d265d29a7db3a1bd1
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2495
Tested-by: jenkins
OpenOCD's SWD subsystem doesn't currently have a consistent WAIT
handling (i.e. it doesn't ever retry, just returns an error), so right
after a row write a small delay is needed as AHB access is stalled
during the flashing operation.
The issue was exposed with a samd20 using ftdi SWD transport.
Change-Id: I07d99d3a96845cc689c3904a41f4d41344f200aa
Signed-off-by: Andrej Kazmin <funnyfish@funnyfish.botik.ru>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2268
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This optional argument tells OpenOCD to exit after finishing (either
succesfully, or with an error) the programming sequence. Without it
OpenOCD stays running.
Change-Id: I6ecaf33ff985eea9a9cd02ff644a74403ae3e1e5
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2492
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Currently
openocd -c "echo a1; shutdown; echo a2"
outputs both "a1" and "a2" and only then shuts down. This patch fixes
it by making shutdown command throw an exception, so unless it's
caught the shutdown will behave as expected.
Change-Id: I764268b3a9046ff3e9717d04095ea0673f1d755a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2511
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Convert the DWT register store to use a byte array and fix the byte order
bug uncovered by that. Also fix an incorrect access of the PC value.
Change-Id: Idb5acab71bdf5a96895c358324b05c335e4d32ca
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2476
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The registers are represented as bit arrays intended to be accessed using
the buf_set_* and buf_get_* functions. Storing the register values in
integers enables accessing them directly, which gives different results
depending on host byte order.
Convert the register store to use a byte array instead and fix all the
byte order bugs uncovered by that.
Also merge the 32 and 64 bit register fields. Only one of them is used at
a time and after the change to byte arrays their types are also the same.
Change-Id: I456869a1737f4b4f5e8ecbfc1c63c49a75d21619
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2475
Tested-by: jenkins
Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is a new driver for Silicon Laboratories SiM3 microcontroller
family, based on the work of Ladislav Bábel. The driver will try to
detect the type of MCU from the device id register, and if this
fails it will use the flash size from the flash bank command.
Driver added to the documentation and to the README.
TCL script added.
Tests:
* Hardware: SiM3C166 (pre-production) and SiM3U167
* Binary: 4kb, 197kb, 256kb
* Flash protect not tested
Change-Id: I701e0cf505ca8ad99be7f83543fe5055b2f65dcc
Signed-off-by: Andreas Bomholtz <andreas@seluxit.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2078
Tested-by: jenkins
On armv7 there no longer are 1kB pages. Instead the bit that in
older architectures distinguished 1kB pages from 4kB pages is on
armv7 used for as execute-never marker. There may now also be 16MB
supersections with 40 bit physical address.
Change-Id: I959bdb8012782a9d07d968907a21f50e3d9b356a
Signed-off-by: Daniel Glöckner <daniel-gl@gmx.net>
Reviewed-on: http://openocd.zylin.com/2386
Tested-by: jenkins
Reviewed-by: Vladimir Svoboda <ze.vlad@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add serial option to jlink config commands, handy when there is more than one
adapter connected.
To select adapter 0123456 for OpenOCD, use
jlink serial 0123456
Change-Id: Ib29ce3f0c4975e1169211721a4531bf4db61f1ee
Signed-off-by: Joerg Fischer <turboj@gmx.de>
Reviewed-on: http://openocd.zylin.com/2521
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add Cortex-A5 identification to ROM-table display, and also
to cortex_a_init_debug_access. This change is mostly cosmetic.
Change-Id: I7b1dd8755d70d45eb5f315aa1918d44a813b3cdf
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/2483
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The image struct is malloc'd and hence base_address_set doesn't have a
defined value.
Caught by Valgrind.
Change-Id: Ice15b2299fc768e44e8034eeb93e035076eacd03
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2524
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
After profiling gmon.out was being written in little endian format only
which would cause gprof to issue and error and exit on big endian targets.
Change-Id: I526a40adae0f9a439fc5b77cef30fda228198b48
Signed-off-by: Jose de Sousa <jose.t.de.sousa@gmail.com>
Reviewed-on: http://openocd.zylin.com/2168
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
adds flash support for Nuvoton M052, M054, M058, M0516 microcontrollers
into the mini51 driver, patch also adds support for programing LDROM,
flash data and flash config.
I've tested it on a M0516LBN microcontroller using an ST-LINK/V2:
1. removing security lock:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "init ; halt ; mini51 chip_erase; exit"
2. flashing:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "program file.hex"
Change-Id: I918bfbb42461279c216fb9c22272d77501a2f202
Signed-off-by: Pawel Si <stawel+openocd@gmail.com>
Reviewed-on: http://openocd.zylin.com/2426
Tested-by: jenkins
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I53568674951ec8a5db5e191c7b50c60b5a84d0b6
Signed-off-by: Michael Brown <fractalmbrown@gmail.com>
Reviewed-on: http://openocd.zylin.com/2463
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
New NOR flash driver was derived from stm32lx.
Procedure ocd_process_reset_inner is overriden in psoc4.cfg
to handle reset halt and system ROM peculiarities.
Change-Id: Ib835324412d106ad749e1351a8e18e6be34ca500
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2282
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Commit 832f0a5bfb 'stm32: add mass erase support for STM32L' added
use of mass-erase in-place of bank-erase. This is triggered if first
bank is requested to be fully erased.
This erroneous action completely fails on STM32L162VEY (has 512 KiB
flash in two 256 KiB banks) and also unintently destroying contents of
EEPROM and second flash bank.
Change-Id: I0f13f7b0346747a09c755d72b5b95775ceff5a6f
Signed-off-by: Jussi Kivilinna <jussi.kivilinna@haltian.com>
Reviewed-on: http://openocd.zylin.com/2441
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Topaz reports on http://sourceforge.net/p/openocd/tickets/87/ that
protection level constants are mixed up. This leads to device ending
up in protection level 1 after mass erase.
Additional work is required to actually put the device in RDP Level 1
and then back to Level 0, as Option bootloader launch is a special
kind of full target reset.
To be able to flash properly after mass_erase a "reset init" is needed
(it's anyway recommended to always perform it before any flash
operation).
Change-Id: I9a838909458039bb0114d3019723bf134fa4d7c9
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2490
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This macro makes windows builds faster and helps with the old "#define
interface struct" issue as the word "interface" is part of libusb-0.1
API. However, defining it in replacements.h is too late, as windows.h
gets included by that time from somewhere else.
This solution is provided by Ray Donnelly from the MSYS2 team.
Change-Id: I376a5fb3d106786515d7e1ba44dbd751e4dcdb1b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2486
Tested-by: jenkins
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since libusb-0.1 might be provided by libusb-compat, it will depend on
libusb-1.0, so needs to be mentioned before it in the link command
line, this is relevant for static linking.
Thanks go to mingwandroid for spotting it during MSYS2 build.
Change-Id: I15cf0b8f084c351b4f93e75686bd0f843477352b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2485
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the new STM32F446 mcu with 512 Ko
Tested with a eval board
Change-Id: I0c16ce7d32d249c7634d697815207c20e7f778c4
Signed-off-by: prudhomme.remi@gmail.com
Reviewed-on: http://openocd.zylin.com/2484
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The message as it was didn't let the user know that something was wrong
with the target or wiring.
Change-Id: Ib609c2d31959e77413e61c348d0e31d7269d5c58
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2365
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Jens Bauer <jens@gpio.dk>
Also remove an unrelated no-op cast.
Change-Id: Ibeb6c72e5b0b0347abb568947a05a179661faf2d
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2473
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This helps to uncover incorrect usage when a pointer to uint32_t is
passed to those functions which leads to subtle bugs on BE systems.
The reason is that it's normally assumed that any uint32_t variable
holds its value in host byte order, but using but_set_u32 on it
silently does implicit pointer conversion to (void *) and the
assumption ends up broken without any indication.
Change-Id: I48ffd190583d8aa32ec1fef8f1cdc0b4184e4546
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2467
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Do not use buf_set_u32 on integers; they're not buffers.
If using buf_set_u32 on integers, bytes will be exchanged on Big Endian targets.
In this particular case, FLASH_OPTCR was incorrectly written, causing it to often
contain one of these values: 0x00aaaae1, 0x00aaffef, 0x00ffabe1 or 0x00abffe1.
This write-protected the device before flash-programming, causing this command...
flash write_image erase unlock myfile.elf
... to fail, complaining about write-protection.
Repeating the above command would change the OPTCR register each time.
After applying this patch, the OPTCR remains "unchanged".
Change-Id: I73d510fcc2e81a01973ad5c6e1aa22715ebd2743
Signed-off-by: Jens Bauer <jens@gpio.dk>
Reviewed-on: http://openocd.zylin.com/2466
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Mass erase operation might be impacted by different factors,
apparently the most reliable way is to do it while asserting the chip
reset line.
Change-Id: Id6ab57eaec86e402ffdf4f5c8843e7735640f03e
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2424
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Enable auto-creating additional discovered TAPs even if some TAPs are
predefined, avoiding initialization failure when it's not necessary.
Also, drop the arbitrary limit on the number of predefined TAPs. Still,
don't auto-create any if there are more than 20 TAPs already, to stop
a noisy connection from creating unlimited TAPs.
Create auto-probed TAPs with less noise.
Reduce code duplication between verification and auto-probing.
Change-Id: I82a504d92dbcc0060206e71f10c5158256b5f561
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The default label does just return the same error code as the case for
zero, so this can be handled by a simple if statement.
Change-Id: I61a8cb51b5e261f21eca386af7d8cbf17ffa2d44
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/2430
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Previously the serial wasn't actually used in hid_open() call,
which meant that the first device with matching vid:pid was opened
irrespective of the actual serial number.
Change-Id: I45216ae5d9e0798e97be693c30e2f03c89b9a02b
Signed-off-by: Jaakko Kukkohovi <jkukkohovi@gmail.com>
Reviewed-on: http://openocd.zylin.com/2487
Tested-by: jenkins
Reviewed-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
As of RM0091, Rev. 7, all F0 have the same revisioning scheme.
Change-Id: I0b344a1d3ca3f61f48fa151e83c549ca5333ae47
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2457
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The ability to change the speed has been added to firmware versions J22 and
above. Any attempt to change on earlier versions will be ignored without error,
as the existing code does.
For supported firmware versions the driver will attempt to get as close as
possible to supported speeds (never higher).
The default stlink speed on power up is 1.8MHz.
The driver will now also print supported clocl speeds during init.
Change-Id: Iee9bd018bb8b6f94672a12538912d41c23d48a7e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2335
Tested-by: jenkins
As a note we need to cache the requested speed setting, as the
hla interface may not be ready when the first adapter_khz is called.
Change-Id: I2fa6807d5f0bd3f0365cf178bd10a230c39415a7
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2334
Tested-by: jenkins
Output a similar message to what we have on low-level JTAG adapters to
avoid confusing users. Reported on IRC by chickensk.
Change-Id: I96d58410ef715b966e32d79c0aacf38596c5eb3f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2451
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Previously the jtag_add_reset(1, 0) caused the processor to be released,
and if SRSTn existed then it would then be reset again two lines later.
Change-Id: I58b7a12607f46f83caa7ed3b3cebc4195eb51ef6
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/2398
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds flash programming support for LPC5410x and LPC82x.
And adds auto flash size detection for LPC800 series.
Tested on below listed boards/chips.
LPC54102(LPCLPC54102Xpresso)
LPC824(LPCXpresso824-MAX)
LPC812(LPC812MAX)
LPC811,LPC810
Change-Id: Ie68b6d425b17ccfa83814607ee61056e99800c1c
Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/2442
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
A7 MPCore needs unlocking the debug registers same as with A15 MPCore.
Found out by hacking on the code.
Change-Id: I613cb4fb35007b85b4a9a401577b47768bc1a08b
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-on: http://openocd.zylin.com/2344
Tested-by: jenkins
Reviewed-by: Kamal Dasu <kamal.dasu@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Added Cortex-A15 support for DAP AHB-AP init code as per ADI V5 spec.
Also added changes to make the APB MEM-AP to work with A15.
Made the the cortex_a target code generic to work with A8, A9
and A15 single core or multicore implementation. Added armv7a code
for os_border calculation to work for known A8, A9 and A15
platforms based on the ARM DDI 0344H, ARM DDI 0407F, ARM DDI 0406C
ARMV7A architecture docs.
Change-Id: Ib2803ab62588bf40f1ae4b9192b619af31525a1a
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1601
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
When no transport is selected, the error message dumps the available
transports, but not how to actually select one.
Change-Id: I63da2a4b59e3f6cc8d30bd631e41a82636a056ef
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2406
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
For example "bp 0x20000000 8 2" makes openocd segfaulting on a
stm32f4x Discovery board.
Change-Id: I1ddd46b1fa9ade78db2234ed975ccefb72539331
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/2342
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
GCC-4.2 on Mac/PPC complains about size_t is expected for %zx and the build stops.
In order to avoid other problems, I've chosen simply to typecast.
Change-Id: I99b569c4d1100e729712e31d24d6539f8b5971b6
Signed-off-by: Jens Bauer <jens@gpio.dk>
Reviewed-on: http://openocd.zylin.com/2360
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
When communication with target fails for whatever reason, it makes
sense to do JTAG-to-SWD (in case the target got power-cycled or the
DAP method was reset anyhow), SWD line reset sequence (part of
JTAG-to-SWD already) and the mandatory IDCODE read. Schedule that to
be performed on the next poll.
Fix the return values for ftdi and jlink drivers to be consistent with
OpenOCD error codes and remove ad-hoc calls to perform DAP method
switching (as it's now done from the upper layer automatically).
Change-Id: Ie18797d4ce7ac43d8249f8f81f1064a2424e02be
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2371
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mateusz Manowiecki <segmentation@fault.pl>
When a target was present on OpenOCD start but later disappeared for
whatever reason (typically unstable connection or target going to
sleep) and reappeared only for a brief period of time, reexamination
would fail, and poll would no longer run. This patch fixes it.
Change-Id: I61f9b5a3f366a761320e233f4e1689f926b5556d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2370
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
The IAP firmware won't return a proper status with some versions. This
happens on my CCC r0ket board and others have seen it as well [1]. So
just ignore the status code and do a (weak) consistency check instead.
[1] http://www.lpcware.com/content/forum/lpc1343-iap-read-part-identification-command
Change-Id: I0daa779d520a540629677c56857bbc20d6db422d
Signed-off-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-on: http://openocd.zylin.com/2364
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The FSF address has changed; The FSF site says that
address is
Free Software Foundation
51 Franklin Street, Fifth Floor
Boston, MA 02110-1301
USA
(see http://www.fsf.org/about/contact/)
Instead of updating it each time the address changes,
just drop it completely treewide.
Change-Id: I27199f7625901f677d8105d1e8876cff00147b71
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2340
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
When an enabled FPU is detected we now use an appropriate stacking.
Change-Id: I1b0f43ec22e1c55c4f10e2ffa97d4aaa77bca5ee
Signed-off-by: Christian Gudrian <christian.gudrian@gmx.de>
Reviewed-on: http://openocd.zylin.com/2354
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
In ChibiOS/RT 3.0 the ready list pointer "rlist" is now part of the system
data structure. Since the ready list is the first element in that
structure it can be accessed via the structure's symbol "ch".
Change-Id: Idc7eaa87cb7bbad0afa0ff1dafd54283bf429766
Signed-off-by: Christian Gudrian <christian.gudrian@gmx.de>
Reviewed-on: http://openocd.zylin.com/2352
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
is_erased can be one of -1, 0, or 1 so it must not be checked like a
boolean value. In this case we want to erase a page unless we know it's
already erased so we just check for is_erased != 1.
Thanks to Jim Paris for pointing this out on another driver.
Change-Id: I4591186228153b64e5a9608a2aac18745e578d4a
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2368
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tim Newsome
Tomas Vanek
SASANO Takayoshi
Steven Stallion
Andreas Fritiofson
Stephen Tridgell
Matthias Welwarsky
Peter A. Bigot
Andreas Bolsch
Uwe Bonnes
Sergey A. Borshch
George Ioakimedes
Olaf Lüke
Andy Pomfret
Andrey Skvortsov
Andreas Färber
Fredrik Hederstierna
Esben Haabendal
Marc Schink
Ivo Manca
Alexander Kurz
Jiri Kastner
Rick Foos
James Mastros
Aleksander Morgado
Robert Jordens
Lieven Hollevoet
Peter D. Gray
Salvador Arroyo
Salvador Arroyo
Jonathan Dumaresq
Ivan Meleca
Evan Hunter
Linus Walleij
Paul Fertser
Colin Helliwell
Alamy Liu
anpilog
Jacob Rosenthal
Kent Brinkley
Matthias Welwarsky
Ivan De Cesaris
Bogdan Kolbov
Peter Lawrence
Matthew Campbell
Patrick Stewart
Oleksij Rempel
Jakub Kubiak
Karl Palsson
Felipe Balbi
Andreas Loehre
Jeff Ciesielski
Morgan Quigley
Mahavir Jain
Thomas Schmid
Jonathan Larmour
Oleksij Rempel
daniel-k
Maxime Coquelin
Andrew Ruder
Alex Forencich
Jim Paris
Nemui Trinomius
Ivan Buliev
Philipp Wagner
Austin Morton
Christoph Pittracher
Andrey Yurovsky
Kyle Manna
Alexander Drozdov
Vincent Palatin
Simon Qian
Spencer Oliver
Richard Braun
Juha Niskanen
Patrick Noffke
Ed Beroset
Uwe Kleine-König
DmitryShpak
Mateusz Manowiecki
Angus Gratton
Franck Jullien
pierre Kuo
Marian Cingel
Olivier Esver
Theodore A. Roth
dmitry pervushin
Robert P. J. Day
Jean-Christian de Rivaz
Matej Kupljen
Christopher Head
Andrej Kazmin
Antony Pavlov
Andreas Bomholtz
Daniel Glöckner
Joerg Fischer
Olivier Schonken
Jose de Sousa
Pawel Si
Michael Brown
Jussi Kivilinna
Rémi PRUD’HOMME
Jens Bauer
Jaakko Kukkohovi
Jörg Wunsch
Alexander Stein
Kamal Dasu
Grigori Goronzy
Christian Gudrian