zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
8,379 Commits
46 Branches
9 Tags
21 MiB
Commit Graph

8379 Commits (b3ddfc70e850fdc58c3a7b5a823b2129c111e7e7)

Author SHA1 Message Date
Tim Newsome 097d62d159 Make delay update messages debug instead of info. 
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
 2018-01-04 13:36:53 -08:00
Megan Wachs 33aad3524b
Add a comment in dbus_read 
This just comments the current behavior
 2018-01-04 13:27:35 -08:00
Tim Newsome 07e19e17cb Use register names instead of numbers in warnings 
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
 2018-01-04 13:27:18 -08:00
Bas Vermeulen ada631cc5f target aarch64: rework memory read/write to use 8/16/32 bit operations 
The existing code only used Memory Access mode to read memory,
which uses 32 bit operations only.
Rework the code to check the alignment/size of the read/write operation,
and use the Memory Access mode to read aligned 32 bit memory.
When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW}
instead.

The exception handling is still the same as it was before (meaning it breaks
when things go wrong), but I can now read an 8 bit register correctly.

Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15
Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Reviewed-on: http://openocd.zylin.com/4301
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
 2018-01-04 09:09:46 +00:00
Tim Newsome 82529e71e0
Merge pull request #170 from riscv/strtoull 
Parse 64-bit CRC addrs even on 32-bit hosts
 2018-01-03 12:48:36 -08:00
Tomas Vanek bb976e3c38 jtag/drivers/cmsis-dap: fix connect under reset 
Commit ef02b69b14 included
a call to cmsis_dap_cmd_DAP_Connect() before calling
cmsis_dap_cmd_DAP_SWJ_Sequence(). According to comment
it is necessary for at least Keil ULINK-ME.

Commit 72c3464be4 added
a cmsis_dap_cmd_DAP_Disconnect() before connect call to pair
connection/disconnection. It solves some problems on Atmel EDBG.

Unfortunately calling either of cmsis_dap_cmd_DAP_Connect()
or cmsis_dap_cmd_DAP_Disconnect() deasserts reset signal.
So these workarounds break ability to connect under reset.

Use cmsis_dap_cmd_DAP_Disconnect() and cmsis_dap_cmd_DAP_Connect()
pair only if both SRST and TRST are deasserted.

Change-Id: I0914dae0a1360b8c7fe48231ff3867caedfb2dbe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reported-by: Leonardo Sabino dos Santos <leonardo.sabino@gmail.com>
Reviewed-on: http://openocd.zylin.com/4100
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
 2018-01-03 10:56:32 +00:00
Tim Newsome 2eddd8e092 Parse 64-bit CRC addrs even on 32-bit hosts 
Change-Id: I38720163eff292b2c24f25da4e25feb8245ff672
 2018-01-02 12:58:46 -08:00
Tim Newsome f822956994
Merge pull request #169 from riscv/unused_boards 
Remove board files that I shouldn't have added
 2018-01-02 12:19:55 -08:00
Tim Newsome 1ddbe70443 Remove board files that I shouldn't have added 
There are 3 other ones for the SiFive target.

Change-Id: I987331a82186a3738096cc390c91889118bf9ac2
 2017-12-29 13:11:27 -08:00
Tim Newsome ab5a98663e
Merge pull request #168 from gnu-mcu-eclipse/sifive-cfg 
Add config files for the SiFive boards
 2017-12-29 11:39:57 -08:00
Liviu Ionescu bd566a98bc add configs for the SiFive boards 
- the HiFive1 board definition includes the FTDI interface
- the Arty boards require external interface definitions
 2017-12-29 17:36:54 +02:00
Tim Newsome 603ed9c419
Merge pull request #167 from riscv/sifive_cfg 
Add config files for SiFive RISC-V hardware.
 2017-12-28 16:34:57 -08:00
Tim Newsome c27a777eb8
Merge pull request #165 from riscv/typo 
Fix typo.
 2017-12-28 16:13:11 -08:00
Tim Newsome 8150358cde Add config files for SiFive RISC-V hardware. 
Copied from https://github.com/gnu-mcu-eclipse/openocd

Change-Id: Ia0b3e192ca8b3bae6035623d605c9980e9bccd2c
 2017-12-28 16:10:41 -08:00
Tim Newsome 52368d6ea1 Fix typo. 
Issue #164

Change-Id: I083ba0d7df72a83a802297baa25753f8d274519a
 2017-12-28 11:52:59 -08:00
Tim Newsome 0774011e21
Merge pull request #163 from riscv/no_abort 
Get rid of abort() calls.
 2017-12-27 14:01:46 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls. 
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
 2017-12-27 13:45:50 -08:00
Tim Newsome d7ed191457
Merge pull request #162 from riscv/no_abort 
Propagate error instead of calling abort().
 2017-12-27 10:00:59 -08:00
Tim Newsome 06445f5743 Propagate error instead of calling abort(). 
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
 2017-12-26 15:04:02 -08:00
Tim Newsome ca700dcef0
Merge pull request #161 from riscv/dead_code 
Remove unused code.
 2017-12-26 14:54:00 -08:00
Tim Newsome 4fa3d819d2 Remove unused code. 
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
 2017-12-26 14:27:44 -08:00
Tim Newsome 561b0c94c0
Merge pull request #160 from riscv/style 
Conform to OpenOCD style guide.
 2017-12-26 14:01:54 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide. 
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
 2017-12-26 11:38:11 -08:00
Tim Newsome 19d9e3e32a
Merge pull request #159 from riscv/update 
Merge changes from master
 2017-12-26 11:37:41 -08:00
Tim Newsome d2c92be73f Merge branch 'master' into update 
Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
 2017-12-22 13:03:58 -08:00
Tim Newsome 6c719f0ab8
Merge pull request #156 from riscv/fespi 
fix fespi flash after registers were renamed.
 2017-12-22 12:00:11 -08:00
Tim Newsome 1f66c7827b Fix flash/run algorithm with new register names 
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
 2017-12-21 16:41:50 -08:00
Tim Newsome fadf2c1b48 Make functions static. Free memory. 
Change-Id: Iadf7b2a926d6d5abc4c8daa2f5620886bcb09b31
 2017-12-21 16:23:46 -08:00
Megan Wachs 33ef457c6a
Merge pull request #155 from riscv/debug_defines 
Update debug_defines to the one used with spike.
 2017-12-21 15:17:43 -08:00
Megan Wachs a81ad34af3
Merge pull request #148 from riscv/macbuild 
Use %ll instead of %L in scanf.
 2017-12-21 15:16:57 -08:00
Tim Newsome 5892b26259 Update debug_defines to the one used with spike. 
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
 2017-12-21 15:05:12 -08:00
Tim Newsome b01075eaa5
Merge pull request #145 from riscv/rbb_win 
Fix Windows build
 2017-12-21 14:04:33 -08:00
Tim Newsome 105536089b
Merge pull request #151 from riscv/use_paren 
Use parens after if.
 2017-12-21 12:50:56 -08:00
Tim Newsome fa385bdcd5 Use parens after if. 
I'm surprised this built with gcc before.

Fixes Issue #150.

Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
 2017-12-21 12:43:22 -08:00
Jiri Kastner 1c2e3d41de config for ESPRESSObin from Globalscale Tech. Inc. 
Change-Id: I77f536a9d2e901ebcef0a7dd0f205e5332b1d382
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/4303
Tested-by: jenkins
Reviewed-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
 2017-12-20 19:47:11 +00:00
Jiri Kastner 84d68579eb configs for Marvell Armada 3700 
Change-Id: I367f39c9bc9e58380d6d5b500d5368d5173d96bd
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/4302
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
 2017-12-20 19:46:20 +00:00
Tim Newsome f13093fff7
Merge pull request #149 from riscv/xml_registers 
Send gdb an XML target description that contains only a list of registers we think exist on this target
 2017-12-19 11:13:19 -08:00
Tim Newsome 11c261cd50 Add `riscv expose_csrs` command. 
This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.

Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
 2017-12-19 10:41:48 -08:00
Tim Newsome 5f86f7208d Hide supervisor registers if there is no S mode. 
Also update encoding.h.

Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
 2017-12-19 10:41:48 -08:00
Tim Newsome f55d1a2030 Give FPRs ABI names. 
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
 2017-12-19 10:41:48 -08:00
Tim Newsome c7cddd2b5c Remove some debug printfs. 
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
 2017-12-19 10:41:48 -08:00
Tim Newsome 56ad0e5b30 Avoid another assertion failure. 
Change-Id: Ia54f778152974164697b712c360918e17a127d95
 2017-12-19 10:41:48 -08:00
Tim Newsome 10c17fdf17 Read misa before using it to check for extensions. 
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
 2017-12-19 10:41:48 -08:00
Tim Newsome ec1c814017 Don't rely on hart count until it's correct. 
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
 2017-12-19 10:41:48 -08:00
Tim Newsome 46715c7d8a Remove no-longer-true comment. 
Change-Id: I888680e73682582438a0de0496238867f1604754
 2017-12-19 10:41:48 -08:00
Tim Newsome 120477b2a2 Simplify examine() 
Now we don't have to play tricks fooling other parts of our code that
might assert.

Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
 2017-12-19 10:41:48 -08:00
Tim Newsome 37278cf2ec Make priv register 8 bits. 
(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)

Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
 2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11. 
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
 2017-12-19 10:41:48 -08:00
Tim Newsome 8926e66d3a Hide unknown registers, which probably don't exist 
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
 2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names. 
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
 2017-12-19 10:41:48 -08:00