* Implement riscv_get_thread_reg().
This is necessary because riscv_get_gdb_reg_list() now reads all
registers, which ended up causing `-rtos riscv` to read all registers
whenever one was requested (because the register cache is wiped every
time we switch to a different hart).
CustomRegisterTest went from 1329s to 106s.
Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32
* Also implement riscv_set_reg().
Now all the `-rtos riscv` tests pass again, at regular speed.
Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1
* Better error messages.
Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5
* Add target_get_gdb_reg_list_noread().
Being explicit about what's expected gets `-rtos riscv` back to `-rtos
hwthread` time.
Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7
* Revert a change I made that has no effect.
I don't understand exactly what all this test protects against, and I
shouldn't change it unless I do.
Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
Currently, the SWD buffer size is adjusted corresponding to the free
device memory. However, the adjusted size is not used.
This fixes SWD operations on devices with small device memory, such as
EFM32PG12 Pearl Gecko STK. It should also fix#184.
Change-Id: I2ec5cf25c62f18bd9e99a2f4aa1aa8d85ed0821b
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4878
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
After commit a6c4eb0345 ("swd: Remove DAP from parameter list")
the global variable jtag_interface is not referenced in the driver.
Remove the extern declaration.
Change-Id: I72018a59c9cecaa52d9a49ec0d7816ac0e656314
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4874
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Before commit 877cec20dc ("command:
check command mode for native jim commands") all the jim commands
were erroneously treated as they had mode COMMAND_ANY.
The commit above fixes the code in order to check the mode and
permit running the commands only if the mode is respected.
Those jim commands that have incorrect mode were not detected nor
fixes because the wrong mode was masked by the missing mode check.
After the commit above, the wrong mode triggers error in several
existing configuration scripts.
A complete list of commands that now does not run anymore as
CONFIG_ANY is reported in ticket 225, but most of them have the
mode set correctly.
At least two instances of command "jtag configure" have the wrong
mode.
Fix the mode to CONFIG_ANY for command "jtag configure" in files
src/jtag/aice/aice_transport.c and src/jtag/tcl.c
Change-Id: I3f96c5fd24d7d463712cbaf1295284fe0dc56b23
Ticket: https://sourceforge.net/p/openocd/tickets/225/
Reported-by: Bill Paul <wpaul@users.sourceforge.net>
Fixes: 877cec20dc ("command: check command mode for native jim commands")
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4886
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Fix "Potential leak of memory pointed to by 'cortex_m'"
and test for NULL return from calloc in cortex_m_target_create()
Change-Id: I4d2bb5bccc57f0ed60696f3d588297a858b8ea60
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4881
Tested-by: jenkins
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added an error msg in case of no memory
Change-Id: I7a7d266ca4aa1e4a0ff02a2d1cc672a3cd2746c3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4882
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added id, name, flash size and RAM size for following parts to samc20_parts[]:
SAMC20N18A
SAMC20N17A
And the following to samc21_parts[]:
SAMC21N18A
SAMC21N17A
Change-Id: Ie8cf1c531a60bfaed6e814d436d232afb89dae3f
Signed-off-by: Kevin Vermilion <kevin.vermilion@gmail.com>
Reviewed-on: http://openocd.zylin.com/4880
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Fix the write only out params TODO on armv7m.c
Fix conditional move depends on uninitialised value.
It was detected while programming a LPC8Nxx with a FTDI adapter.
valgrind --leak-check=full --show-leak-kinds=all --track-origins=yes
[...]
==8696== Conditional jump or move depends on uninitialised value(s)
==8696== at 0x16E4D3: buf_set_u32 (binarybuffer.h:52)
==8696== by 0x16E4D3: ftdi_swd_queue_cmd (ftdi.c:1206)
==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271)
==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382)
==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420)
==8696== by 0x197CD9: target_write_buffer_default (target.c:2176)
==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383)
==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330)
==8696== by 0x19D846: target_run_algorithm (target.c:814)
==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818)
==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696== by 0x185BDF: flash_driver_erase (core.c:44)
==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696== by 0x18650D: flash_iterate_address_range (core.c:567)
==8696== by 0x18732F: flash_erase_address_range (core.c:584)
==8696== by 0x18732F: flash_write_unlock (core.c:928)
==8696== Uninitialised value was created by a heap allocation
==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299)
==8696== by 0x220EF9: init_mem_param (algorithm.c:30)
==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777)
==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696== by 0x185BDF: flash_driver_erase (core.c:44)
==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696== by 0x18650D: flash_iterate_address_range (core.c:567)
==8696== by 0x18732F: flash_erase_address_range (core.c:584)
==8696== by 0x18732F: flash_write_unlock (core.c:928)
==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457)
==8696== by 0x1B7D99: run_command (command.c:623)
==8696== by 0x1B7D99: script_command_run (command.c:208)
==8696== by 0x1B7FD9: command_unknown (command.c:1033)
==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364)
==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814)
==8696==
==8696== Conditional jump or move depends on uninitialised value(s)
==8696== at 0x16E506: buf_set_u32 (binarybuffer.h:52)
==8696== by 0x16E506: ftdi_swd_queue_cmd (ftdi.c:1207)
==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271)
==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382)
==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420)
==8696== by 0x197CD9: target_write_buffer_default (target.c:2176)
==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383)
==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330)
==8696== by 0x19D846: target_run_algorithm (target.c:814)
==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818)
==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696== by 0x185BDF: flash_driver_erase (core.c:44)
==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696== by 0x18650D: flash_iterate_address_range (core.c:567)
==8696== by 0x18732F: flash_erase_address_range (core.c:584)
==8696== by 0x18732F: flash_write_unlock (core.c:928)
==8696== Uninitialised value was created by a heap allocation
==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299)
==8696== by 0x220EF9: init_mem_param (algorithm.c:30)
==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777)
==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696== by 0x185BDF: flash_driver_erase (core.c:44)
==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696== by 0x18650D: flash_iterate_address_range (core.c:567)
==8696== by 0x18732F: flash_erase_address_range (core.c:584)
==8696== by 0x18732F: flash_write_unlock (core.c:928)
==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457)
==8696== by 0x1B7D99: run_command (command.c:623)
==8696== by 0x1B7D99: script_command_run (command.c:208)
==8696== by 0x1B7FD9: command_unknown (command.c:1033)
==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364)
==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814)
Change-Id: I50f9a8c4516b686cf62ac3c76f47c53465e949da
Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
Reviewed-on: http://openocd.zylin.com/4811
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Adds ability to change the user data in STM32F1x/STM32F3x MCU's option byte.
Since OpenOCD prints the content of user data in option byte registers, it
is seems logical to also provide a way how to change this data.
Change-Id: Ie6cb756b4f11b5c6dabd34bc89434a358eb758ff
Signed-off-by: Jan Vojtech <honza.vojtech@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4663
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Without this change xxx_start_algorithm() writes all register
parameters no matter of their direction. It usually results
in writing of uninitialized reg_params[].value - possibly
reported by valgrind.
While on it fix the wrong parameter direction in
kinetis_disable_wdog_algo(). This bug did not have any
impact because of unconditional write of reg_params.
Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4813
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The comment above the function is correct, but the code set
the GPIO with wrong (reversed) polarity.
Change-Id: Ifd09688150d3d2018af73521e0da3926bb1b7f84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4847
Tested-by: jenkins
Reviewed-by: Grzegorz Kostka <kostka.grzegorz@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
With this patch drivers will be able to use usb path filtering.
The path format is identical to the format provided by linux kernel:
bus-port.port....
With this format it should be easier just to copy and paste
path found in dmesg.
Change-Id: I8bafa6fcb7a66ff68cc961a376f97f4f3dee35aa
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/4580
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The new Microchip (former Atmel) series powered by Cortex-M4 looks
very similar to older M0+ powered SAM D2x at the first sight.
Unfortunately the new series differs a lot in important details.
NVMCTRL has different register addresses, moved important bits
and even changed binary command set. An universal driver for all SAM D/E
would be very complicated. That's why a new driver was derived.
Tested on Microchip SAM E54 Xplained Pro kit (board cfg included).
Adjusted for the restructured dap support.
Checked by valgrind and clang static analyzer.
Change-Id: I26c67047a552076f4b207b9b89285a53d69b4ca4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4272
Tested-by: jenkins
Reviewed-by: Andres Vahter <andres.vahter@gmail.com>
stm32x_write_options() uses stm32x_write_block() at STM32_OB_RDP address.
The change eliminates subtracting bank->base (and later adding it back).
Change-Id: Icdd24afc7178b814be58e6033d4b93fdfb2d2a16
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4859
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Change-Id: I1e9e62979c4629c8ba1d5ae89ca7392259969eb6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4858
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Stepping in the maskisr auto mode sets breakpoint to step over interrupt
service tasks. If the device has FPB rev 1, setting hard breakpoint
is impossible on address over 0x1fffffff.
Use soft type breakpoint for adresses over 0x1fffffff if FPB is rev 1.
This may eventually fail if the code memory is not writeable, but there
is nothing to do in such case.
Change-Id: Ibdeeb506903a35d550b64f82c24c37a668de62b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4857
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
samr34/r35 combine SAML21 and SX1276 (lora transceiver). This one was found on
xplaned pro evaluation kit. Ids for other r34/r35 chips are apparently not yet
documented.
Change-Id: I4054dd56ea53c9bae8d17abd5a3e4e65e1b9c8b1
Signed-off-by: Guillaume Revaillot <g.revaillot@gmail.com>
Reviewed-on: http://openocd.zylin.com/4872
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
See #202. I don't have a proper target with >32-bit flash and memory
location, so I've been unable to properly test this. However, if I hack
the fespi driver to not do anything and run the 64-bit spike tests I can
see that the memory map OpenOCD sends now includes the full 64-bit
address space:
Debug: 3443 975 gdb_server.c:400 gdb_put_packet_inner(): sending packet
'$l<memory-map>
<memory type="ram" start="0x00000000" length="0x20000000"/>
<memory type="ram" start="0x20000000" length="0xffffffffe0000000"/>
</memory-map>
It will also do this when the target is 32-bit, but that doesn't seem to
have any ill effects on gdb.
Change-Id: I0fd070ab7366188ff0259d90386f5e1f6985ce21
The functions dap_to_jtag() and dap_to_swd() have been introduced by
3ef9beb52c ("ADIv5 DAP ops switching to JTAG or SWD modes") in
arm_adi_v5.c by using the JTAG queue only.
Later, in 6f8b8593d6 ("ADIv5 transport support moves to separate
files") the functions has been moved in adi_v5_swd.c and adi_v5_jtag.c
but keeping the dependency from JTAG queue.
The functions does not work if the current transport is not JTAG.
Move back the functions in arm_adi_v5.c, replace the input parameter
"target" with "dap", use the transport to detect if the JTAG queue is
present, in case of SWD transport use the proper method, for other
transports report error.
Reuse the ADI v5 sequences already present in jtag/swd.h.
Also, OpenOCD does not support switching to another transport after
the initial selection, so do not change DAP's ops vector.
Change-Id: Ib681fbaa60cb342f732bc831eb92de25afa4e4db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4852
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Treat ARM_MODE_SYS like all other Aarch32 processor modes,
except for the special case of missing SPSR.
Change-Id: I60b21703659b264f552884cdc0f85fd45f7836de
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4494
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
A target created after init lacks target_init_one() call
and is not added to gdb targets.
Steps to reproduce:
- start OpenOCD with a dap target
- connect by telnet
target create ap0.mem mem_ap -dap $_CHIPNAME.dap -ap-num 0
reset
Segmentation fault is rised because target->check_reset is NULL.
Change-Id: I2a62f3b450e4db3005c7041a22fb8f952e68c3b6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4842
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The command mode was checked only for simple type of commands.
Native commands (handled by jim_handler) was treated as
they had mode COMMAND_ANY
Change-Id: Iab1d8cbb0b8c6f6b9f3cf942600432dec9a703ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4841
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Commit 44009186cf added logging
of failed cmd name but it used c->name only. It might be confusing:
Debug: 244 105 command.c:644 run_command(): Command 'init' failed with error
code -4
User : 245 106 command.c:711 command_run_line():
Debug: 246 107 command.c:644 run_command(): Command 'init' failed with error
code -4
The command on line 244 is 'dap init'
Use full name of cmd including parents.
Change-Id: Iff131ce6454ef70b353ce1bc6d0a480b92820545
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4837
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
Without this change TARGET_DEBUG_RUNNING changes to TARGET_RUNNING
after adapter_poll()
Change-Id: I1c965a43527b50fa723d78fb6eae56585a7ede03
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4820
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
All the commands in OpenOCD have been inspected and have the
command mode initialize, apart for two of them.
This is not critical, because the uninitialized value (0) is
equivalent to the enum COMMAND_EXEC, that is also the correct
value for the two mentioned commands.
To keep the code consistent, initialize the command mode to
COMMAND_EXEC.
Change-Id: Iaf043364cbd1005418d787ed045a3ec653612382
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4861
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The original script was broken by changes to the Cortex-A code. The
recent introduction of the mem_ap target provided a new mechanism to
allow the script to be fixed. This also adds an example board script
for the ADSP-SC584-EZBRD.
Change-Id: I36bc1ac6b6c036539f4175f1e65223ba10a35355
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: http://openocd.zylin.com/4855
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
While connecting under reset, use the already defined macro
SWJ_PIN_SRST to assert the srst pin.
Change-Id: Icebed462c0fe8f8c15f6522dc56625aa580b8858
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4846
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add RTOS task awareness for Chromium-EC. Currently
only supports ARM Cortex-M0/M3/M4 based targets.
No new Clang Analyzer warnings.
Change-Id: Iea56fcb1be220e2437613922879b63d6e553703d
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/4685
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.
Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The encoding of BKPT instruction is 0xE12###7#, where the four '#'
characters should be replaced by the 16 bits immediate value.
The macro uses an incorrect shift amount, thus the immediate value
is not properly coded and bits 20~23 of the opcode could get
corrupted.
Fixed by using the proper shift amount.
Change-Id: I32db8224ab57aad6d3b002f92f9f259056593675
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4854
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Fix the SWD line reset sequence accordingly to Arm specification IHI
0031E that requires at least 2 idle clocks after the 50 clocks with
SWDIO high.
Fix the value of the activation code in the (currently unused)
sequence dormant-to-SWD.
Make each sequence's length multiple of 8, so it is compatible with
adapters that have such limitation (e.g. buspirate) and try to split
and comment each part of the sequence (when possible keep each part
byte aligned, inspired from commit 3ef9beb52c). This slightly
increases the sequence length but does not impact run-time
performance because these are rarely used sequences.
Add the missing sequence dormant-to-JTAG and JTAG-to-dormant, not
used yet.
On devices that implements the dormant state, IHI 0031E deprecates
the direct switching between SWD and JTAG, and recommends using a
transition through dormant. This is not implemented.
Change-Id: Iad18c0e736cfd9366be175d22658d664b0c61eab
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4851
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This hardware id is e.g. used by the Insight SiP ISP1507-AX.
Change-Id: I82568d292f9882372ab061d8e3e36906b0cc5882
Signed-off-by: Mirko Vogt <mirko.vogt@sensorberg.com>
Reviewed-on: http://openocd.zylin.com/4845
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Previously the code made the assumption (which is valid for conventional
RTOSs) that special registers (e.g. CSRs) are the same across threads.
26/45 tests pass.
Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
This patch covers the fact that cortex_m could be resumed externally by
Cross Trigger Interface or by direct write to DHSCR ...
To reproduce:
- halt the target
- then run the core through DHCSR (mww 0xe000edf0 0xa05f0001)
=> this resumes the core, but target state in OpenOCD remains HALTED.
Change-Id: Ifa1ae18645bfeb863acc78a039bbf04873fd78fe
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4817
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tim Newsome
Marc Schink
Antonio Borneo
Oleksij Rempel
Tomas Vanek
Kevin Vermilion
Jean-Christian de Rivaz
Jan Vojtech
Guillaume Revaillot
Matthias Welwarsky
Peter Lawrence
Moritz Fischer
Jonathan McDowell
Mirko Vogt
Tarek BOCHKATI