97ea54030c
Merge pull request #87 from riscv/gdb_next_port
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When gdb_port is 0, don't increment it.
2017-08-08 10:01:26 -07:00
b897807224
When gdb_port is 0, don't increment it.
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Usually incrementing to get the next port is a good idea, but when set
to 0 the idea is to find an arbitrary unallocated port. 1 is almost
certainly not helpful.
2017-08-07 13:55:37 -07:00
b9822ab1b8
Merge pull request #86 from riscv/debug
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Display register numbers in a more usable format.
2017-07-27 14:49:29 -07:00
46b5f913c7
Display register numbers in a more usable format.
2017-07-27 13:45:26 -07:00
73dee3ad4a
Merge pull request #85 from riscv/print_port
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Print out which port OpenOCD is listening on.
2017-07-26 07:51:37 -07:00
753d15e22c
Print out which port OpenOCD is listening on.
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This is essential when a test environment asks OpenOCD to listen on port
0, so that the environment can easily discover which port is actually
being used.
2017-07-25 14:08:10 -07:00
79329f21a3
Merge pull request #84 from riscv/reset
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Fix infinite loop in reset.
2017-07-16 12:47:41 -07:00
b032eb1bcc
Use a wall clock timeout to complete reset.
2017-07-16 11:48:12 -07:00
f0f1df1061
Fix infinite loop in reset.
2017-07-14 12:50:11 -07:00
43c6fd3b8f
Merge pull request #83 from riscv/triggers
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Share trigger code between 0.11 and 0.13 code.
2017-07-13 18:04:34 -07:00
d60dbd60e8
Share trigger code between 0.11 and 0.13 code.
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The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.
In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
cc2c2e7a65
Merge pull request #82 from riscv/comment
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Forgot to commit this follow up to PR #79
2017-07-12 19:45:40 -07:00
2deb02695e
Forgot to commit this follow up to PR #79
2017-07-12 17:51:38 -07:00
46b91c9b0d
Merge pull request #79 from riscv/abstract_regs
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Use abstract command to access registers if possible
2017-07-12 17:50:46 -07:00
09bf86e31a
Keep around cmderr for callers to inspect.
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Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
856f70fe44
Try abstract register writes as well.
2017-07-12 14:13:31 -07:00
f37e93bbc0
Try using abstract commands to read registers
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This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.
Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).
riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)
2017-07-12 14:13:31 -07:00
da74f511b9
Merge pull request #80 from riscv/triggers
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Disable debugger-set triggers on connect
2017-07-11 12:13:56 -07:00
a0c1dd643a
Merge pull request #81 from riscv/llp64
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Use LL for 64-bit defines, as Windows is LLP64
2017-07-10 16:00:39 -07:00
10a61000b5
Use LL for 64-bit defines, as Windows is LLP64
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This should also fix bugs on ILP32 systems.
2017-07-10 13:45:42 -07:00
4072fa493b
Disable debugger-set triggers on connect
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When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.
To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.
Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
29b62710f7
Merge pull request #78 from riscv/build32
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Add 32-bit build
2017-07-06 15:03:12 -07:00
21e06e1d89
Fix 32-bit build.
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Code taken from http://openocd.zylin.com/#/c/4178/
2017-07-06 14:53:28 -07:00
708b05ba07
Build 32- and 64-bit binaries with Travis.
2017-07-06 14:53:14 -07:00
31e5b53a46
Merge pull request #74 from riscv/build32
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Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
9f1738ae49
Merge pull request #77 from riscv/travis
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Perform regular build with travis.
2017-07-06 10:54:34 -07:00
3be99ac884
Perform regular build with travis.
2017-07-05 10:33:42 -07:00
321619946b
Merge pull request #73 from riscv/old_triggers
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Add back support for type 1 triggers
2017-07-03 13:52:16 -07:00
3cff4213a4
Merge pull request #69 from riscv/multi-gdb
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Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
ce48a5d3da
Merge pull request #72 from dmitryryzhov/examine_restore_temp_reg
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Restore value of temporary register (s0) in examine OpenOCD procedure…
2017-07-03 12:43:47 -07:00
450307b66f
Fix 32-bit build errors.
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I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71 .
2017-07-03 12:17:07 -07:00
f18fd83ac7
Fix trigger set/clear bug.
2017-07-03 11:52:35 -07:00
6c627e9ea9
Add back support for type 1 triggers.
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They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
2017-07-03 11:01:10 -07:00
99a3673507
Fix comment about saving the temporary register in examine procedure.
2017-07-01 15:09:23 +03:00
7d451e00f5
Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction.
2017-06-30 19:15:58 +03:00
b6f8efbf44
Check for errors in read_csr().
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Also slightly improve debugging output.
2017-06-27 15:11:06 -07:00
d77c4a953c
Don't set breakpoints on disabled harts
2017-06-21 12:25:20 -07:00
689d0fcaf6
No longer hard-code the non-RTOS hart to 0
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I was just being lazy here.
2017-06-21 12:25:19 -07:00
4bdb042224
Allow memory writes to proceed on all harts
2017-06-21 12:25:19 -07:00
a277416a39
Refactor examine, to avoid some assertions
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Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart. Those assertions
aren't sane very early in examine, so I avoid them.
2017-06-21 12:25:19 -07:00
788908fcf0
Factor out checking if harts should be used
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Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled". This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
9f4cac5a38
Set current_hartid from coreid
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This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
4e2e730abe
Merge pull request #68 from riscv/multicore
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Testsuite now passes on multicore target
2017-06-20 14:20:00 -07:00
9cd98058a0
Set hardware triggers on all harts.
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Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
10518351bb
Don't immediately segfault with -rtos on v0.11.
2017-06-20 11:32:42 -07:00
ccdd26e3ef
Comment curious code.
2017-06-20 11:32:42 -07:00
927f9d8873
Update list of "threads" when harts are discovered.
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This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00
8d79a7c18b
Merge pull request #67 from riscv/cosmetics
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Various cosmetic improvements
2017-06-20 11:32:17 -07:00
4d264b3579
Put early DEBUG notice of XLEN back.
2017-06-19 08:46:02 -07:00
6082f35a55
Update debug_defines. Clarify debug output.
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Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
2017-06-16 14:02:25 -07:00
Tim Newsome
Palmer Dabbelt
Dmitry Ryzhov