* WIP upstream review feedback.
See http://openocd.zylin.com/#/c/4656/
The main change is to get rid of macros that contain a return statement.
Change-Id: Iff79a8aa7c40ee04a8d1f07d973f9b29d4899d5c
* Remove unaligned head/tail code.
From inspection it's not clear to me that this is necessary at all. I've
been unable to make a test case that results in anything besides a
4-byte aligned flash to happen. Sections that aren't multiples of 4 are
common, and appear to work fine.
Change-Id: Idb6109ca015ae06b9d8f16bd883f9c8f5c51087d
* Move fespi native code into contrib/loaders
As suggested by http://openocd.zylin.com/#/c/4656/
Change-Id: I275012aa8a1ef6a0e8a2ec8ebe8643d87de24407
* Reenable hw mode if errors happen without it.
Change-Id: I1220033c13d02e8a441992bd6daa0ec3b5acbfca
* Default flash to not protected.
Requested by upstream review.
Change-Id: I61753bd9909d7f21ef6624037a865072c18bd1d8
* Install patchutils for the build.
This contains filterdiff, which we need to check that our changes
conform to OpenOCD style.
Change-Id: Id522f4e62fee3efad4e0e00933abfeada9635624
* Fix paths for filterdiff line.
Change-Id: Ic50e13c7fe64e65b2d2af0260fb19c07a9f10e20
* Conform to OpenOCD style.
Change-Id: I51660d30404c0a625b58c9bed2d948695575e72e
This fixes the following error, that has been reported occasionally:
Error: 34072 2712 riscv-011.c:1175 reg_cache_get(): Register cache entry for 0 is invalid!
openocd: ../src/target/riscv/riscv-011.c:1176: reg_cache_get: Assertion `r->valid' failed.
The problem was that we'd tell the target to step, and then gdb (which
assumed the target halted already) asked to read a register before the
target had actually halted. With this fix the target is actually halted,
and everything works.
Change-Id: Icfcef456f3cec4bb352fb90186f5bbabb00a5ff8
* Changed logging level
* Added logging statement
* Removed halt event when attaching to target
* Extended some packet handling
* Extended handling of rtos_hart_id and clearing of register cache
* Extended execute_fence to handle all harts
* Removing logging statement again
* Updated according to review comments
* Forgot to re-add the return statement
* Was removing too much for the if statement to work
* This needs to >= 3 now to handle both a fence and a fence.i
I think that libusb_handle_events_timeout_completed is supposed to make
progress or time out, but sometimes we hit a case where it makes no
progress, and mpsse_flush() loops forever. This wall clock timeout kicks
it out of that loop. OpenOCD appears to die afterwards, but that's still
an improvement.
Change-Id: Id9220557625834fb5b7dccf65251651a11a887f0
The repo.or.cz version is often unavailable.
Presumably we want to do something similar for the other submodules, but I didn't find as obvious official mirrors for those.
* Added `riscv expose_custom` command.
Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.
Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f
* Conform to OpenOCD style.
Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf
* Free all the memory allocated by register init.
Change-Id: I04e35ab54613f99708cee85e41fef989079adefc
* Properly document `riscv expose_custom`.
Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
In my test-case (64-bit OpenOCD, 64-bit target), OpenOCD ended up
sending gdb '$T05rwatch:1212340a00;thread:0000000000000002#89'
That's missing the final semi-colon after the thread id.
This fix increases the buffer size, and also removes the 0 padding on
the thread id.
This bug showed up when running MulticoreRtosSwitchActiveHartTest
against dual-hart, 64-bit spike.
Change-Id: I8c7d88e2d37b00cf3099f226a1a32671219802d5
* Add riscv_hit_watchpoint function for RV32I loads and stores
For GDB to fully support hardware watchpoints, OpenOCD needs to tell GDB
which data address has been hit. OpenOCD relies on a target-specific
hit_watchpoint function to do this. If GDB is not given the address, it
will not print the hit variable name or its old and new value.
There does not seem to be a way for the hardware to tell us which trigger
was hit (0.13 introduced the 'hit bit' but this is optional). Alternatively,
we can decode the instruction at dpc and find out which memory address
it accesses.
This commit adds support for RV32I load and store instructions
and could be extended for additional instructions in the future.
* 0.11: change debug reason for hw triggers to DBG_REASON_WATCHPOINT
This is to make sure riscv_hit_watchpoint is called to check for a data
address hit.
* Fix style issues
* Change %lx to PRIx64 to clear -m32 build errors
* Add clarifying comments/todos
* Fix types in format strings
Tim Newsome
Greg Savin
Pavel S. Smirnov
Carsten Gosvig
cgsfv
Megan Wachs
Ryan Macdonald
Ryan Macdonald
Andrew Waterman
Andrew Waterman
craigblackmore