Flash loaders refactored to the new style - use generated .inc
instead of hexadecimal machine code in the flash driver source.
Change-Id: If65a2099589e210f9450819b467d67819fd841fc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4439
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The "Blue Pill" is a popular development board with an STM32F103C8
micro controller. According to sources, it has a 128kB Flash on board
even though the option bytes only report 64kB. This patch therefore also
modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into
account which the board file sets to 0x20000.
Change-Id: I8a78ccd2b5faf637c539ee3cf8136789ee15c95d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4495
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tell git to give us 20 lines of context, which hopefully is enough to
deal with some spurious warnings.
Change-Id: I97cb572f7b89ff305f46290d20ed0b4674af1f5b
* Enforce OpenOCD style guide.
Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8
* Fail if `git diff` fails
Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9
* Maybe every line gets its own shell?
Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6
* Maybe this will error properly.
Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9
* Take different approach than merge-base
Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1
* Fix style issues.
Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
Add configuration for the Renesas R-Car R8A7790 H2 target.
This is an SoC with four Cortex A15 and four Cortex A7
ARMv7a cores, only the four A15 cores are supported.
Change-Id: I6099b257cc0f04e6858ed5f5f8c8d8ad82ef7650
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4490
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Minor fix, no code change, just align it to the block it belongs to.
Change-Id: I4c3b0d0bd00a55d5109d3723e5c4bfb2fc72e366
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4492
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Instead of trying to predict exactly how many steps will be required
(doable but error-prone), just allocate more memory when we need it.
Tested against HiFive1, and Arty board image.
Change-Id: I3cd9798432e65176616c700ba122daf7a5ed6209
The Vybrid VF6xx SoCs contain an additional Cortex-M4
core connected to AP number 3 of the main DAP.
Change-Id: I59c020fdfc53e909b1f0dac1a8627a62cdaa74f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3640
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Cortex-M target used 'auto_bp_type' mode. The requested type
of breakpoint was ignored and hard (FPB) breakpoints were set in
'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above
0x20000000.
The code memory area of Cortex-M does not mean the memory is flash and
vice versa. External flash (parallel or QSPI) is usually mapped above
code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis
has a RAM block under 0x20000000 boundary.
Remove 'auto_bp_type' mode, set breakpoints to requested type.
Change 'cortex_m maskisr auto' handling to use a hard temporary
breakpoint everywhere: it can also workaround not working soft breakpoints
on Cortex-M7 with ICache enabled.
Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4429
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Bohdan Tymkiv
Tomas Vanek
Matthias Welwarsky
Tim Newsome
Megan Wachs
Marek Vasut
Ryan Macdonald
Antonio Borneo