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7690 Commits (689d0fcaf6764b6a8efbbfed51e048a94c03f3bf)

Author SHA1 Message Date
Tim Newsome 32e7a962c3 Write fence.i before dret. 
Makes things work if the ROM doesn't contain fence.i (which is slow, so
Andrew took it out).
 2016-09-23 14:16:23 -07:00
Tim Newsome 4ced71b1f1 Log more. 2016-09-23 14:16:23 -07:00
Tim Newsome 20e2bfe3db Quickly read all GPRs on halt. 
gdb will ask for them anyway, and one by one is slow.
StepTest went from 9.7s to 5.3s.
 2016-09-23 14:16:23 -07:00
Tim Newsome 6fac5a41f8 Remove some hwbp debug code. 2016-09-23 14:16:23 -07:00
Tim Newsome 7dcc0681d4 Speed up some other operations. 2016-09-23 14:16:23 -07:00
Tim Newsome 1fdcfa7082 Speed up register read. 
Don't scan an extra sequence just to read the return value.
 2016-09-23 14:16:23 -07:00
Tim Newsome 27b94d36d0 Fix 32-bit build. 2016-09-23 14:16:23 -07:00
Tim Newsome 668070cc45 Faster download. 
16K testcase:
Transfer rate: 53 KB/sec, 2222 bytes/write.
 2016-09-23 14:16:23 -07:00
Tim Newsome 9aab0aa068 Minor cleanup. 2016-09-23 14:16:23 -07:00
Tim Newsome 06f6b5020c Use optimized cache/program write scheme for most 
operations.
 2016-09-23 14:16:23 -07:00
Tim Newsome a1875fbecf Working on optimized program running. 
Makes a big difference on the XLEN code (29ms to 8ms). Now to use it in
more places.
 2016-09-23 14:16:23 -07:00
Tim Newsome 9b9653ab7d Use hardware single step. 2016-09-23 14:16:23 -07:00
Tim Newsome eac8933b89 WIP on performance improvement. 
Also implement empty arch_state to prevent occasional startup crash.
 2016-09-23 14:16:23 -07:00
Tim Newsome 2d02e77bed Make this compile for 32-bit targets. 2016-09-23 14:16:23 -07:00
Tim Newsome aaa8ce10b8 Correctly figure out the number of extant hwbps. 2016-09-23 14:16:23 -07:00
Tim Newsome c471cfb63b Simple execute hardware breakpoint works. 2016-09-23 14:16:23 -07:00
Tim Newsome cb57aa55fa Deal with exceptions on register read. 
Cache dpc, so we can restore it when it's clobbered by an exception.
 2016-09-23 14:16:23 -07:00
Tim Newsome b81a846be5 Cache dcsr, since we're reading it anyway. 2016-09-23 14:16:23 -07:00
Tim Newsome c8430bb8f4 DebugTest.test_interrupt passes now. 2016-09-23 14:16:23 -07:00
Tim Newsome e10d407623 Speed up memory read a little. 2016-09-23 14:16:23 -07:00
Tim Newsome 4b19b7305f Save/restore T0 around block writes. 2016-09-23 14:16:23 -07:00
Tim Newsome 90f458e63f Reading/writing s1 now works. 2016-09-23 14:16:23 -07:00
Tim Newsome 0881092d9b Can successfully run to a swbp. 2016-09-23 14:16:23 -07:00
Tim Newsome c364bd0ab5 We can run to a software breakpoint, but 
gdb doesn't notice we're halted once we hit it, even though riscv_poll()
is setting the target state to halted.
 2016-09-23 14:16:23 -07:00
Tim Newsome 04cfc35147 Use the dram cache to save some scans. 2016-09-23 14:16:23 -07:00
Tim Newsome dce4a992a3 Single memory reads/writes work. 2016-09-23 14:16:23 -07:00
Tim Newsome 39788e5e6b Fix typo in comment. 2016-09-23 14:16:23 -07:00
Tim Newsome 1b349df638 WIP hackery. 
Main thing I added is code to output "verilog" for every JTAG op we do,
so we can run the same thing in simulation.
 2016-09-23 14:16:23 -07:00
Tim Newsome f40862d87c Go through run-test/idle once per dbus access. 2016-09-23 14:16:23 -07:00
Tim Newsome 9f22176618 Reading registers appears to work. 2016-09-23 14:16:23 -07:00
Tim Newsome 84944ded87 Fix up some register stuff. 
Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
 2016-09-23 14:16:23 -07:00
Tim Newsome f634702aaf Successfully determine xlen. 
There's a nop in there for no reason, though.
 2016-09-23 14:16:23 -07:00
Tim Newsome db06dd45a0 Improve error checking. 2016-09-23 14:16:23 -07:00
Tim Newsome 40e42c5a04 Print out really long scan values. 2016-09-23 14:16:22 -07:00
Tim Newsome 63f6999b6d Print idcode value in error message. 2016-09-23 14:16:22 -07:00
Tim Newsome 041e0ccf9e Selecting dbus is sometimes necessary. 2016-09-23 14:16:22 -07:00
Tim Newsome 25e8b66b08 WIP registers. 2016-09-23 14:16:22 -07:00
Tim Newsome ae74097f39 Add extra debug output. 
This probably shouldn't be in the final change list.
 2016-09-23 14:16:22 -07:00
Tim Newsome 3b60c3aa42 Fix bug when waiting for debugint to clear. 2016-09-23 14:16:22 -07:00
Tim Newsome 67009979ae Clearer debug logging. 2016-09-23 14:16:22 -07:00
Tim Newsome 3b3beb04ef WIP on registers. 2016-09-23 14:16:22 -07:00
Tim Newsome 330ff8b2c9 Try to document struct reg. 2016-09-23 14:16:22 -07:00
Tim Newsome 482497c51a Blind implementation of write_memory. 2016-09-23 14:16:22 -07:00
Tim Newsome 50ca8ac373 Blind implementation of read_memory. 2016-09-23 14:16:22 -07:00
Tim Newsome 76fe7db0db In theory assert_reset/deassert_reset work. 2016-09-23 14:16:22 -07:00
Tim Newsome ea6836c5f6 WIP, blind coding. 2016-09-23 14:16:22 -07:00
Tim Newsome 413ab49dfd Blind coding new dbus behavior. 2016-09-23 14:16:22 -07:00
Tim Newsome feff2dd9e7 Always leave the TAP in Run-Test/Idle. 2016-09-23 14:16:22 -07:00
Tim Newsome 98f2fa897f Halt should work now. 2016-09-23 14:16:22 -07:00
Tim Newsome bb0463deec Set up dram structure; implement poll(). 2016-09-23 14:16:22 -07:00